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公开(公告)号：US07281136B2
公开(公告)日：2007-10-09
申请号：US09779440
申请日：2001-02-09
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
摘要翻译： 在LSI设计中采用加密处理，以便改进电路设计数据对传统示例的保密性。 在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。 将加密的设计数据提供给进行设计/验证处理的用户。 钥匙也按要求提供。 在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。 在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。
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公开(公告)号：US20080028233A1
公开(公告)日：2008-01-31
申请号：US11601776
申请日：2006-11-20
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
摘要翻译： 在LSI设计中采用加密处理，以便改进电路设计数据与传统示例的机密性。 在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。 将加密的设计数据提供给进行设计/验证处理的用户。 钥匙也按要求提供。 在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。 在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。
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公开(公告)号：US20070011468A1
公开(公告)日：2007-01-11
申请号：US11520712
申请日：2006-09-14
IPC分类号： G06F12/14
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
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公开(公告)号：US07148503B2
公开(公告)日：2006-12-12
申请号：US09968898
申请日：2001-10-03
CPC分类号： H01L23/5382 , G06F15/7867 , G06F17/5045 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/15192 , H01L2924/3011 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.
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公开(公告)号：US20060275932A1
公开(公告)日：2006-12-07
申请号：US11496574
申请日：2006-08-01
IPC分类号： H01L21/00
CPC分类号： H01L23/5382 , G06F15/7867 , G06F17/5045 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/15192 , H01L2924/3011 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.
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6.发明授权Method for improving the efficiency of designing a system-on-chip integrated circuit device 有权提高片上系统集成电路器件设计效率的方法公开(公告)号：US06415416B1
公开(公告)日：2002-07-02
申请号：US09418312
申请日：1999-10-14
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool. In this manner, a power and clock management module for use in power save management, a wrapper bank select module storing interconnection information, a shared resource module storing information about a sharable resource and an optimized top-level hierarchy module storing interconnection information about an optimized top-level hierarchy are generated. Downsizing and power saving are realized by resource sharing and power management.
摘要翻译： 关于多个块中的排他性操作的信息和关于每个这些块内的可共享资源的互连信息被定义。 基于可共享资源信息和块间专用操作信息，提取在块之间可共享的资源。 存储关于接口，功耗，操作模型和顶级层级互连的信息的模块规格，描述块之间的排他性操作规则的排他性操作信息，以及用于防止各功能在相同功能中被使能的优先功能信息 时间被输入到作为自动生成工具的发电机。 以这种方式，用于节电管理的电源和时钟管理模块，存储互连信息的封装器组选择模块，存储关于可共享资源的信息的共享资源模块和存储关于优化的互连信息的优化顶层层级模块 生成顶级层次结构。 资源共享和电源管理实现了小型化和省电化。
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公开(公告)号：US06886150B2
公开(公告)日：2005-04-26
申请号：US10067820
申请日：2002-02-08
CPC分类号： G06F17/5045
摘要： Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool. In this manner, a power and clock management module for use in power save management, a wrapper bank select module storing interconnection information, a shared resource module storing information about a sharable resource and an optimized top-level hierarchy module storing interconnection information about an optimized top-level hierarchy are generated. Downsizing and power saving are realized by resource sharing and power management.
摘要翻译： 关于多个块中的排他性操作的信息和关于每个这些块内的可共享资源的互连信息被定义。 基于可共享资源信息和块间专用操作信息，提取在块之间可共享的资源。 存储关于接口，功耗，操作模型和顶级层级互连的信息的模块规格，描述块之间的排他性操作规则的排他性操作信息，以及用于防止各功能在相同功能中被使能的优先功能信息 时间被输入到作为自动生成工具的发电机。 以这种方式，用于节电管理的电源和时钟管理模块，存储互连信息的封装器组选择模块，存储关于可共享资源的信息的共享资源模块和存储关于优化的互连信息的优化顶层层级模块 生成顶级层次结构。 资源共享和电源管理实现了小型化和省电化。
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8.发明授权Method of designing integrated circuit device using common parameter at different design levels, and database thereof 有权使用不同设计级别的公共参数设计集成电路器件的方法及其数据库公开(公告)号：US06671857B1
公开(公告)日：2003-12-30
申请号：US09638397
申请日：2000-08-15
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： The method for designing an integrated circuit device of the present invention includes the steps of: obtaining the number of operations by a functional simulation; determining a specification model based on the number of operations; determining an behavioral model corresponding to the specification model based on the number of operations per cycle required; determining a RTL model corresponding to the behavioral model based on the number of operations per cycle required; and obtaining design data corresponding to the RTL model for implementing the function.
摘要翻译： 本发明的集成电路装置的设计方法包括以下步骤：通过功能模拟获得操作次数; 基于操作次数确定规格模型; 基于所需的每个周期的操作次数来确定与规范模型相对应的行为模型; 基于每个周期所需的操作次数确定与行为模型相对应的RTL模型; 并获取与实现该功能的RTL模型对应的设计数据。
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9.发明授权ID installable LSI, secret key installation method, LSI test method, and LSI development method 有权ID安装LSI，秘密密钥安装方法，LSI测试方法和LSI开发方法公开(公告)号：US07284134B2
公开(公告)日：2007-10-16
申请号：US10231376
申请日：2002-08-30
申请人： Makoto Fujiwara , Akira Motohara
发明人： Makoto Fujiwara , Akira Motohara
IPC分类号： G06F11/30
CPC分类号： G06F21/73 , G11C7/24 , G11C17/14 , G11C29/027 , G11C29/12 , G11C2029/5002
摘要： In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.
摘要翻译： 在LSI中，解码部对从外部接收的ID信号进行解码，并输出解码信号。 当操作设置信号有效时，熔丝电路将解码信号表示的值写入其中，并且当操作设置信号无效时保持写入值。 ID RAM将保存在熔丝电路中的值作为ID存储。 这样可以通过改变ID信号的值来在LSI中安装各种ID的ID。
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10.发明申请ID installable LSI, secret key installation method, LSI test method, and LSI development method 审中-公开ID安装LSI，秘密密钥安装方法，LSI测试方法和LSI开发方法公开(公告)号：US20080046759A1
公开(公告)日：2008-02-21
申请号：US11889676
申请日：2007-08-15
申请人： Makoto Fujiwara , Akira Motohara
发明人： Makoto Fujiwara , Akira Motohara
IPC分类号： G06F21/02
CPC分类号： G06F21/73 , G11C7/24 , G11C17/14 , G11C29/027 , G11C29/12 , G11C2029/5002
摘要： In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.
摘要翻译： 在LSI中，解码部对从外部接收的ID信号进行解码，并输出解码信号。 当操作设置信号有效时，熔丝电路将解码信号表示的值写入其中，并且当操作设置信号无效时保持写入值。 ID RAM将保存在熔丝电路中的值作为ID存储。 这样可以通过改变ID信号的值来在LSI中安装各种ID的ID。
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