公开(公告)号：US20240428875A1

公开(公告)日：2024-12-26

申请号：US18749161

申请日：2024-06-20

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Hajime SANO ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Kazuma HASEGAWA

IPC: G11C29/38 ,  G06F13/16

Abstract: A system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. The host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. The host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.

公开(公告)号：US20250095756A1

公开(公告)日：2025-03-20

申请号：US18821402

申请日：2024-08-30

Applicant: Kioxia Corporation

Inventor： Hajime SANO

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/12

Abstract: A semiconductor memory device includes memory cell transistors and a control circuit. The control circuit is configured to set a threshold voltage of each memory cell transistor to be in one of voltage ranges to store multi-bit data in each memory cell transistor. The voltage ranges include a first range corresponding to a first multi-bit value, a second range lower than the first range and corresponding to a second multi-bit value, and a third range that is the lowest. When a target memory cell transistor in which data of the second multi-bit value is to be written currently stores data of the first multi-bit value, the control circuit is configured to apply a first voltage to a gate of the target memory cell transistor, to shift the threshold voltage of the target memory cell transistor to be in the second range without dropping into the third range.