公开(公告)号：US20230282289A1

公开(公告)日：2023-09-07

申请号：US17899447

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Masayuki MIURA ,  Yoshihiro OHBA

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  H01L27/11563

CPC classification number: G11C16/26 ,  G06F3/0679 ,  G11C16/34 ,  H01L27/11563

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

公开(公告)号：US20220011963A1

公开(公告)日：2022-01-13

申请号：US17197667

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Yuta AIBA ,  Hitomi TANAKA ,  Masayuki MIURA ,  Mie MATSUO ,  Toshio FUJISAWA ,  Takashi MAEDA

IPC: G06F3/06

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

公开(公告)号：US20240428875A1

公开(公告)日：2024-12-26

申请号：US18749161

申请日：2024-06-20

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Hajime SANO ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Kazuma HASEGAWA

IPC: G11C29/38 ,  G06F13/16

Abstract: A system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. The host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. The host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.

公开(公告)号：US20220091772A1

公开(公告)日：2022-03-24

申请号：US17410674

申请日：2021-08-24

Applicant: KIOXIA CORPORATION

Inventor： Toshio FUJISAWA ,  Tomoya SANUKI ,  Hitomi TANAKA ,  Takeshi ISHIHARA ,  Yasuhito YOSHIMIZU

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory with a plurality of blocks. A controller in the system controls the writing of data to the non-volatile semiconductor memory and includes a host I/F control interface to receive write command information including file allocation information indicating a location for write data, a file information management unit to assign an erasure level to a file and output a file identifier in which a file name, a file size, and the erasure level of the file are combined, and a flash translation layer unit to allocate each file on a single file per block basis based on the write command information and the file identifier.