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公开(公告)号：US20240321352A1
公开(公告)日：2024-09-26
申请号：US18603281
申请日：2024-03-13
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Hidehiro SHIGA , Daisaburo TAKASHIMA
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0064
Abstract: According to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. The sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.
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公开(公告)号：US20220108729A1
公开(公告)日：2022-04-07
申请号：US17495747
申请日：2021-10-06
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Daisaburo TAKASHIMA , Takahiko IIZUKA
Abstract: According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.
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公开(公告)号：US20230413584A1
公开(公告)日：2023-12-21
申请号：US18231304
申请日：2023-08-08
Applicant: Kioxia Corporation
Inventor： Takahiko IIZUKA , Daisaburo TAKASHIMA , Ryu OGIWARA , Rieko FUNATSUKI , Yoshiki KAMATA , Misako MOROTA , Yoshiaki ASAO , Yukihiro NOMURA
CPC classification number: H10B63/845 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C2213/75 , H10B63/34 , H10N70/066 , H10N70/231 , H10N70/8828 , G11C13/0069
Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
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公开(公告)号：US20220028452A1
公开(公告)日：2022-01-27
申请号：US17443586
申请日：2021-07-27
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Daisaburo TAKASHIMA , Takahiko IIZUKA
Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.
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公开(公告)号：US20240038279A1
公开(公告)日：2024-02-01
申请号：US18359355
申请日：2023-07-26
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Hidehiro SHIGA , Daisaburo TAKASHIMA
Abstract: According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.
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Patent Agency Ranking
公开(公告)号：US20220109024A1
公开(公告)日：2022-04-07
申请号：US17495103
申请日：2021-10-06
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Daisaburo TAKASHIMA , Takahiko IIZUKA
Abstract: According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.
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公开(公告)号：US20210399049A1
公开(公告)日：2021-12-23
申请号：US17348839
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Takahiko IIZUKA , Daisaburo TAKASHIMA , Ryu OGIWARA , Rieko FUNATSUKI , Yoshiki KAMATA , Misako MOROTA , Yoshiaki ASAO , Yukihiro NOMURA
Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
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公开(公告)号：US20210090647A1
公开(公告)日：2021-03-25
申请号：US17022580
申请日：2020-09-16
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Daisaburo TAKASHIMA , Takahiko IIZUKA
IPC: G11C13/00
Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.
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公开(公告)号：US20220367568A1
公开(公告)日：2022-11-17
申请号：US17877714
申请日：2022-07-29
Applicant: Kioxia Corporation
Inventor： Ryu OGIWARA , Daisaburo TAKASHIMA , Takahiko IIZUKA
Abstract: A memory device includes a memory cell and a first select transistor. The memory cell includes a variable resistance memory region, a first semiconductor layer being in contact with the variable resistance memory region, a first insulating layer being in contact with the first semiconductor layer, and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes a second semiconductor layer, a second insulating layer being in contact with the second semiconductor layer, and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.
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公开(公告)号：US20210287733A1
公开(公告)日：2021-09-16
申请号：US17015408
申请日：2020-09-09
Applicant: Kioxia Corporation
Inventor： Takahiko IIZUKA , Daisaburo TAKASHIMA , Ryu OGIWARA
IPC: G11C11/4096 , G11C11/4094 , G11C11/4074 , G11C11/408 , G11C5/02 , G11C5/06
Abstract: According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.
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