公开(公告)号：US20240105275A1

公开(公告)日：2024-03-28

申请号：US18460486

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Kiyoe YAMASAWA ,  Yasuyuki MATSUDA

IPC: G11C29/12

CPC classification number: G11C29/12015 ,  G11C16/0483

Abstract: A latch group includes a first latch circuit, a second latch circuit, and a third latch circuit. A clock signal of which a signal value is inverted from a clock signal of the second latch circuit is input to the first latch circuit and the third latch circuit. A control circuit is configured to operate the latch group in a normal mode, and first and second test modes. The control circuit, while operating the latch group in a first test mode, transmits a control signal to the first switch circuit to connect the electrical path between the first data output terminal and the second data input terminal, and while operating the latch group in the second test mode, transmits a control signal to the second switch circuit to connect the electrical path between the second data output terminal and the third data input terminal.

公开(公告)号：US20220366973A1

公开(公告)日：2022-11-17

申请号：US17874968

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Yasuyuki MATSUDA

IPC: G11C11/56 ,  G11C11/408 ,  G11C16/08

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

公开(公告)号：US20230206998A1

公开(公告)日：2023-06-29

申请号：US18112507

申请日：2023-02-22

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Yasuyuki MATSUDA

IPC: G11C11/56 ,  G11C11/408 ,  G11C16/08

CPC classification number: G11C11/5628 ,  G11C11/4085 ,  G11C11/565 ,  G11C16/08 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

公开(公告)号：US20220270691A1

公开(公告)日：2022-08-25

申请号：US17459572

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Yousuke TAMURA ,  Yasuyuki MATSUDA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A semiconductor storage device includes a plurality of planes, the planes including a first plane and a second plane, an interface circuit configured to receive and transmit control signals for the planes, and a control circuit configured to control the planes based on the control signals. While a first operation that includes multiple loops of a high voltage operation and a verify operation is being performed by the first plane, the control circuit controls the second plane to perform a second operation during at least one period in which the verify operation is performed by the first plane.