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17 条记录 (耗时 0.04 秒)

    ERROR CONTROL CODE APPARATUSES AND METHODS OF USING THE SAME
    3.
    发明申请
    ERROR CONTROL CODE APPARATUSES AND METHODS OF USING THE SAME 有权
    错误控制代码设备及其使用方法

    公开(公告)号：US20080276150A1

    公开(公告)日：2008-11-06

    申请号：US11905734

    申请日：2007-10-03

    申请人： Jun Jin KONG ,  Seung-Hwan SONG ,  Dong Hyuk CHAE ,  Kyoung Lae CHO ,  Seung Jae LEE ,  Nam Phil JO ,  Sung Chung PARK ,  Dong Ku KANG

    发明人： Jun Jin KONG ,  Seung-Hwan SONG ,  Dong Hyuk CHAE ,  Kyoung Lae CHO ,  Seung Jae LEE ,  Nam Phil JO ,  Sung Chung PARK ,  Dong Ku KANG

    IPC分类号： G06F11/08

    CPC分类号： G06F11/1072

    摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

    摘要翻译： 应用于多电平单元（MLC）方法的存储器的错误控制代码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。 另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

    MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING
    4.
    发明申请
    MEMORY DEVICE AND METHOD FOR ESTIMATING CHARACTERISTICS OF MULTI-BIT PROGRAMMING 有权
    用于估计多位编程特性的存储器件和方法

    公开(公告)号：US20120069654A1

    公开(公告)日：2012-03-22

    申请号：US13303353

    申请日：2011-11-23

    申请人： Kyoung Lae CHO ,  Seung-Hwan Song ,  Yoong Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

    发明人： Kyoung Lae CHO ,  Seung-Hwan Song ,  Yoong Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C29/00 ,  G11C2211/5634

    摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

    摘要翻译： 提供了可以估计多位单元特性的存储器件和/或方法。 存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。 由此，可以监视存储单元的阈值电压随时间的变化。

    NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME 失效
    非易失性存储器件，存储卡和系统以及确定读取电压的方法

    公开(公告)号：US20100118608A1

    公开(公告)日：2010-05-13

    申请号：US12614545

    申请日：2009-11-09

    申请人： Seung-Hwan SONG ,  Jaehong KIM ,  Kyoung Lae CHO ,  Yong June KIM ,  Jun Jin KONG ,  Jong Han KIM

    发明人： Seung-Hwan SONG ,  Jaehong KIM ,  Kyoung Lae CHO ,  Yong June KIM ,  Jun Jin KONG ,  Jong Han KIM

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

    摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

    摘要翻译： 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

    MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA
    6.
    发明申请
    MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA 审中-公开
    存储器控制器，包括其的数据存储系统，处理数据的方法

    公开(公告)号：US20120131266A1

    公开(公告)日：2012-05-24

    申请号：US13301961

    申请日：2011-11-22

    申请人： Kyoung Lae CHO ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jin Kyu Kim

    发明人： Kyoung Lae CHO ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jin Kyu Kim

    IPC分类号： G06F12/00

    CPC分类号： G06F12/04 ,  G06F2212/401

    摘要： A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile memory device configured to store the data compressed by the controller and information about whether the data has been compressed. The controller includes a buffer configured to temporarily store the data and the data information received from the host, an analyzer configured to output, based on an analysis result, a compression control flag that indicates whether the data has been compressed, and a compressor configured to selectively compress or bypass the data based on the compression control flag, and to transmit the data to the nonvolatile memory device.

    摘要翻译： 数据存储系统包括控制器，被配置为从主机接收关于数据的数据和数据信息，分析数据信息，检测数据是否已被压缩，并根据检测结果压缩数据; 以及非易失性存储装置，被配置为存储由所述控制器压缩的数据以及关于所述数据是否被压缩的信息。 所述控制器包括被配置为临时存储从所述主机接收到的数据和数据信息的缓冲器，分析器，被配置为基于分析结果输出指示所述数据是否已被压缩的压缩控制标志，以及压缩器， 基于压缩控制标志选择性地压缩或旁路数据，并将数据发送到非易失性存储器件。

    Semiconductor Memory Systems that Include Data Randomizers and Related Devices, Controllers and Methods
    10.
    发明申请
    Semiconductor Memory Systems that Include Data Randomizers and Related Devices, Controllers and Methods 审中-公开
    包含数据随机器和相关器件，控制器和方法的半导体存储器系统

    公开(公告)号：US20120215963A1

    公开(公告)日：2012-08-23

    申请号：US13303512

    申请日：2011-11-23

    申请人： Yong June KIM ,  Jung Soo CHUNG ,  Jun Jin KONG ,  Kyoung Lae CHO

    发明人： Yong June KIM ,  Jung Soo CHUNG ,  Jun Jin KONG ,  Kyoung Lae CHO

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F13/16 ,  G11C7/1006

    摘要： A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period.

    摘要翻译： 半导体存储器系统及其编程方法。 半导体存储器系统包括：具有存储区域的半导体存储器件; 用于控制半导体存储器件的存储区域的编程和读取的存储器控​​制器; 至少一个第一随机化器，用于通过在第一周期中使用第一序列来将要被编程到所述存储区域中的程序数据改变为第一随机数据; 以及至少一个第二随机化器，用于通过在与第一周期不同的第二周期中使用第二序列来将第一随机数据改变为第二随机数据。