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    Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby
    5.
    发明授权
    Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby 有权
    制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法

    公开(公告)号：US07508048B2

    公开(公告)日：2009-03-24

    申请号：US10758802

    申请日：2004-01-15

    申请人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

    发明人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

    摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

    摘要翻译： 提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。 该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。 初始高压栅绝缘层形成为比焊垫绝缘层厚。 形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层 形成衬底以限定第二区域中的第二有源区。 然后去除焊盘绝缘层以露出第一有源区。 在暴露的第一有源区上形成低压栅极绝缘层。 因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域 。

    Flash memory device and method of making same
    6.
    发明授权
    Flash memory device and method of making same 失效

    公开(公告)号：US06515329B2

    公开(公告)日：2003-02-04

    申请号：US10068483

    申请日：2002-02-05

    申请人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

    发明人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.

    Flash memory device and method of making same
    7.
    发明授权
    Flash memory device and method of making same 失效
    闪存设备及其制作方法

    公开(公告)号：US06380032B1

    公开(公告)日：2002-04-30

    申请号：US09724152

    申请日：2000-11-28

    申请人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

    发明人： Won-Hong Lee ,  Sung-Nam Chang ,  Kyu-Charn Park

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.

    摘要翻译： 提供了一种非易失性闪存设备和制造非易失性闪存设备的方法。 共同的源极线与堆叠晶体管的形成同时形成。 公共源极线由与浮动栅极图案相同的材料层形成。 在半导体衬底中通过相同的光刻工艺同时形成公共源极区域和划线区域。 此外，通过相同的光刻工艺，共同的源极线和对接的触点被图案化。 因此，可以以非常低的成本和简单性有利地完成公共源线处理。

    Method for fabricating floating gate
    8.
    发明授权
    Method for fabricating floating gate 有权
    浮栅制造方法

    公开(公告)号：US06482728B2

    公开(公告)日：2002-11-19

    申请号：US10053792

    申请日：2002-01-18

    申请人： Kwang-Shik Shin ,  Sung-Nam Chang ,  Jae-Woo Kim

    发明人： Kwang-Shik Shin ,  Sung-Nam Chang ,  Jae-Woo Kim

    IPC分类号： H01L218247

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed over the conductive layer. Next, a photoresist pattern is formed over the hard mask layer. The hard mask layer is etched to form a hard mask pattern, using the photoresist pattern as an etching mask. The upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact, using the photoresist pattern as an etching mask. The slope-etched upper portion of the conductive layer is again vertically etched and the lower portion of the conductive layer is concurrently slope-etched, using the hard pattern as an etching mask. With the present invention, a bridge between floating gates can be reduced, and field loss can be reduced during processing steps such as an ONO etching process.

    摘要翻译： 提供了一种在非易失性存储器件中制造浮动栅极的方法和使用其制造的浮动栅极。 具有上部和下部的导电层形成在其中形成有场区的衬底上。 在导电层上形成硬掩模层。 接下来，在硬掩模层上形成光致抗蚀剂图案。 蚀刻硬掩模层以形成硬掩模图案，使用光致抗蚀剂图案作为蚀刻掩模。 导电层的上部被斜蚀刻，使用光致抗蚀剂图案作为蚀刻掩模留下导电层的下部完整。 再次垂直蚀刻导电层的斜面蚀刻的上部，并且使用硬图案作为蚀刻掩模，同时对导电层的下部进行斜面蚀刻。 利用本发明，可以减少浮置栅极之间的桥，并且可以在诸如ONO蚀刻工艺的处理步骤期间减小场损耗。

    Non-volatile memory devices and methods of fabricating the same
    10.
    发明授权
    Non-volatile memory devices and methods of fabricating the same 有权

    公开(公告)号：US06891222B2

    公开(公告)日：2005-05-10

    申请号：US10160875

    申请日：2002-05-30

    申请人： Dong-Chan Kim ,  Sung-Nam Chang

    发明人： Dong-Chan Kim ,  Sung-Nam Chang

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Non-volatile memory devices and fabrication methods thereof are provided. The device includes a plurality of isolation layers formed at a semiconductor device, a plurality of stacked gates crossing over an active region between the isolation layers, and an oxidation barrier layer covering the stacked gate. Each of the stacked gates has a control gate electrode crossing over the active region, a floating gate interposed between the control gate electrode and the active region, and an inter-gate dielectric layer interposed between the control gate electrode and the floating gate. Also, the inter-gate dielectric layer has a bottom dielectric layer, an intermediate dielectric layer and a top dielectric layer which are sequentially stacked. The oxidation barrier layer is formed prior to a subsequent thermal oxidation process for curing etch damage that occurs during formation of the stacked gates.