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    VERTICAL MEMORY DEVICE
    2.
    发明申请
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20180122819A1

    公开(公告)日：2018-05-03

    申请号：US15465355

    申请日：2017-03-21

    Applicant: JAE JOO SHIM ,  SEONG SOON CHO ,  JI HYE KIM ,  KYUNG JUN SHIN

    Inventor： JAE JOO SHIM ,  SEONG SOON CHO ,  JI HYE KIM ,  KYUNG JUN SHIN

    IPC: H01L27/11568 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573

    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

    MEMORY DEVICE
    6.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20150054058A1

    公开(公告)日：2015-02-26

    申请号：US14530638

    申请日：2014-10-31

    Applicant: Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    Inventor： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    IPC: H01L27/115 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

    Abstract translation: 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20060216891A1

    公开(公告)日：2006-09-28

    申请号：US11422592

    申请日：2006-06-06

    Applicant: Jung-Dal CHOI ,  Jong-Woo PARK ,  Seong-Soon CHO ,  Chang-Hyun LEE

    Inventor： Jung-Dal CHOI ,  Jong-Woo PARK ,  Seong-Soon CHO ,  Chang-Hyun LEE

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    Abstract: A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

    Abstract translation: 非易失性存储器件包括依次层叠的隧道氧化物层，电荷存储层，阻挡绝缘层和栅电极，以及栅电极两侧的有源区中的杂质扩散层。 栅电极跨越形成在半导体衬底的预定区域中的器件隔离层之间的有源区，并且电荷存储层的边缘延伸成具有从栅电极突出的突出部分。 为了形成具有突出部分的电荷存储层，在形成在衬底中的器件隔离层之间的有源区域中形成包括第一至第三绝缘层的叠层绝缘层。 在堆叠绝缘层上形成与激活区交叉的多个栅电极，并且在栅电极的两个侧壁上形成侧墙。 使用侧壁间隔物和栅电极，对叠层绝缘层进行蚀刻以形成从栅电极的侧壁突出的电荷存储层。

    Vertical memory device
    8.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US10790294B2

    公开(公告)日：2020-09-29

    申请号：US15465355

    申请日：2017-03-21

    Applicant: Jae Joo Shim ,  Seong Soon Cho ,  Ji Hye Kim ,  Kyung Jun Shin

    Inventor： Jae Joo Shim ,  Seong Soon Cho ,  Ji Hye Kim ,  Kyung Jun Shin

    IPC: H01L27/1157 ,  H01L27/11568 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573

    Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

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