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    Method of estimating a leakage current in a semiconductor device
    1.
    发明授权
    Method of estimating a leakage current in a semiconductor device 有权
    估计半导体器件中漏电流的方法

    公开(公告)号：US08156460B2

    公开(公告)日：2012-04-10

    申请号：US12547729

    申请日：2009-08-26

    申请人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    发明人： Kyung-Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a method of estimating a leakage current in a semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of a cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function of a segment is generated by arithmetically operating the virtual cell leakage characteristic functions of all cells in the segment. Then, a full chip leakage characteristic function of the chip is generated by statistically operating the segment leakage characteristic functions of all segments in the chip. Accordingly, computational loads of Wilkinson's method for generating the full chip leakage characteristic function can remarkably be reduced.

    摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际泄漏特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中所有单元的虚拟单元泄漏特性函数进行算术运算，产生段的段泄漏特性函数。 然后，通过统计操作芯片中所有段的段泄漏特性函数来产生芯片的全芯片泄漏特性功能。 因此，Wilkinson用于产生全芯片泄漏特性功能的方法的计算负载可以显着降低。

    Method of Estimating a Leakage Current in a Semiconductor Device
    2.
    发明申请
    Method of Estimating a Leakage Current in a Semiconductor Device 有权
    估算半导体器件中泄漏电流的方法

    公开(公告)号：US20100058258A1

    公开(公告)日：2010-03-04

    申请号：US12547729

    申请日：2009-08-26

    申请人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    发明人： Kyung Tae Do ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Young-Hwan Kim ,  Hyo-Sig Won ,  Wook Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.

    摘要翻译： 在估计半导体器件中的漏电流的方法中，包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。 然后，通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。 因此，威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。

    METHOD OF DESIGNING A SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF DESIGNING A SEMICONDUCTOR DEVICE 失效
    设计半导体器件的方法

    公开(公告)号：US20120297349A1

    公开(公告)日：2012-11-22

    申请号：US13458516

    申请日：2012-04-27

    申请人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    发明人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

    摘要翻译： 在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。 可以设置偏置数据以改变所选择的晶体管的特性。 可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。 可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

    Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices
    4.
    发明授权
    Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices 失效
    设计半导体器件的方法和修改半导体器件布局的方法

    公开(公告)号：US08621399B2

    公开(公告)日：2013-12-31

    申请号：US13458516

    申请日：2012-04-27

    申请人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    发明人： Kyung-Tae Do ,  Yong-Seok Lee ,  Hyo-Sig Won ,  Jung-Yun Choi ,  Jong-Ho Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.

    摘要翻译： 在设计半导体器件的方法中，可以选择包括在半导体器件的布局中的晶体管。 可以设置偏置数据以改变所选择的晶体管的特性。 可以在忽略偏置数据之后执行用于半导体器件的布局的设计规则检查（DRC）处理。 可以基于偏置数据执行用于半导体器件的布局的光学邻近校正（OPC）处理。

    Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same
    5.
    发明授权
    Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same 有权
    具有有源时钟屏蔽结构的电路和包括其的半导体集成电路

    公开(公告)号：US08013628B2

    公开(公告)日：2011-09-06

    申请号：US12381431

    申请日：2009-03-12

    申请人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

    发明人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H04B15/02 ,  H04B2215/064

    摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

    摘要翻译： 具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于 电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对 信号传输线。

    Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same
    6.
    发明申请
    Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same 有权
    具有有源时钟屏蔽结构的电路和包括其的半导体集成电路

    公开(公告)号：US20090237107A1

    公开(公告)日：2009-09-24

    申请号：US12381431

    申请日：2009-03-12

    申请人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

    发明人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

    IPC分类号： H03K19/003 ,  H04B15/00

    CPC分类号： H04B15/02 ,  H04B2215/064

    摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

    摘要翻译： 具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于 电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对 信号传输线。

    Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chip
    7.
    发明授权
    Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chip 有权
    设计片上系统的方法，包括无无线标准单元，设计系统和片上系统

    公开(公告)号：US08522188B2

    公开(公告)日：2013-08-27

    申请号：US13626121

    申请日：2012-09-25

    申请人： Hyung-Ock Kim ,  Jae-Han Jeon ,  Jung-Yun Choi ,  Kee-Sup Kim ,  Hyo-Sig Won

    发明人： Hyung-Ock Kim ,  Jae-Han Jeon ,  Jung-Yun Choi ,  Kee-Sup Kim ,  Hyo-Sig Won

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F2217/84 ,  H01L27/0207

    摘要： In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

    摘要翻译： 在设计片上系统的方法中，包括应用了身体偏置的无电话标准单元，通过反转向前的方式，调整慢转角定时参数以增加片上系统的运行速度分布的缓慢的转角 主体偏置和快速转角定时参数被调整，以通过反射反向主体偏置来减小片上系统的运行速度分布的快速转角。 基于对应于增加的慢转角的调整的慢转角定时参数和对应于减小的快速拐角的经调整的快速角定时参数，实现包括无tapless标准单元的片上系统。 慢转角定时参数对应于片上系统的运行速度设计窗口的最低值，快速转角定时参数对应于片上系统的运行速度设计窗口的最高值。