公开(公告)号：US11710519B2

公开(公告)日：2023-07-25

申请号：US17368705

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Cheng-Lin Sung ,  Yung-Feng Lin

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/102 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US12198752B2

公开(公告)日：2025-01-14

申请号：US18206422

申请日：2023-06-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Cheng-Lin Sung ,  Yung-Feng Lin

IPC: G11C16/28 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US11081595B1

公开(公告)日：2021-08-03

申请号：US16877518

申请日：2020-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Lin Sung ,  Pei-Ying Du ,  Hang-Ting Lue

IPC: G11C16/04 ,  H01L29/788 ,  G11C11/56 ,  H01L29/792

Abstract: A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

公开(公告)号：US11551072B2

公开(公告)日：2023-01-10

申请号：US16872404

申请日：2020-05-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Lin Sung ,  Teng-Hao Yeh

IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C16/26 ,  G11C16/24

Abstract: A spiking neural networks circuit and an operation method thereof are provided. The spiking neural networks circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of memory cells, one word line, a plurality of source lines and a plurality of source line transistors. The page buffers provides a plurality of data signals. Each of the bit line transistors is electrically connected to one of the page buffers. Each of the bit lines receives one of the data signals. The source line transistors are connected together. The neuron circuit is for outputting a feedback pulse.