公开(公告)号：US12245428B2

公开(公告)日：2025-03-04

申请号：US17575418

申请日：2022-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H01L21/786

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

公开(公告)号：US12245413B2

公开(公告)日：2025-03-04

申请号：US17695943

申请日：2022-03-16

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh

IPC: H01L27/11 ,  H10B10/00

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

公开(公告)号：US12094518B2

公开(公告)日：2024-09-17

申请号：US17988760

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C11/40 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4087

Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

公开(公告)号：US20240282386A1

公开(公告)日：2024-08-22

申请号：US18172308

申请日：2023-02-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: G11C16/24 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483

Abstract: A memory device, such as a three-dimensional AND or NOR flash memory includes a memory cell block, multiple first bit line switches, multiple second bit line switches, a first switch, and a second switch. The memory cell block is divided into a first sub memory cell block and a second sub memory cell block. The first bit line switches are respectively coupled to multiple first local bit lines and commonly coupled to a first sub global bit line. The second bit line switches are respectively coupled to multiple second local bit lines and commonly coupled to a second sub global bit line. The first switch is coupled between the first sub global bit line and a global bit line and controlled by a first control signal. The second switch is coupled between the second sub global bit line and the global bit line and controlled by a second control signal.

公开(公告)号：US20240234339A9

公开(公告)日：2024-07-11

申请号：US17972953

申请日：2022-10-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC: H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.

公开(公告)号：US20230368841A1

公开(公告)日：2023-11-16

申请号：US17742148

申请日：2022-05-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh ,  Chih-Chang Hsieh

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

公开(公告)号：US11710519B2

公开(公告)日：2023-07-25

申请号：US17368705

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Cheng-Lin Sung ,  Yung-Feng Lin

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/102 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US11605431B2

公开(公告)日：2023-03-14

申请号：US17325243

申请日：2021-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

公开(公告)号：US11289152B2

公开(公告)日：2022-03-29

申请号：US17077795

申请日：2020-10-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Ming-Liang Wei ,  Po-Kai Hsu ,  Hang-Ting Lue ,  Teng-Hao Yeh

IPC: G11C7/16 ,  G11C11/4091 ,  G06F9/38 ,  G11C11/4076 ,  G11C11/408 ,  G11C16/26 ,  G11C11/54 ,  G11C7/10

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

公开(公告)号：US10741247B1

公开(公告)日：2020-08-11

申请号：US16449158

申请日：2019-06-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/26 ,  G06F7/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A 3D memory array device includes blocks, bit lines, word lines, source lines (SL), complementary metal oxide semiconductors (COMS), and SL sensing amplifiers (SA). Each block includes NAND strings, and each memory cell in the NAND strings stores one or more weights. The bit lines are respectively coupled as signal inputs to string select lines in all blocks. The word lines are respectively coupled to the memory cells, and the word lines in the same layer are as a convolution layer to perform a convolution operation on the inputted signal. Different SL are coupled to all ground select lines in different blocks to independently collect a total current of the NAND strings in each block. The CMOS are disposed under the blocks and coupled to each source line for transferring the total current to each SL SA, and a multiply-accumulate result of each block is outputted via each SL SA.