Abstract:
Systems and techniques relating to angle of arrival (AoA) reverse locationing include: transmitting, by a first wireless device to a second wireless device, one or more reverse tracking service discovery messages via a wireless communication link; receiving, at the first wireless device from the second wireless device, one or more response messages associated with the one or more reverse tracking service discovery messages, wherein the one or more response messages comprise (i) information indicating that the second wireless device is enabled for reverse tracking, and (ii) angle of arrival (AoA) information based on AoA calculations performed by the second wireless device; and determining, by the first wireless device, a location of the second wireless device based on the received AoA information.
Abstract:
Improvements associated with determining a location of a station device are described. According to one improvement, a method is performed by a network device. The method includes receiving a response packet from a station device, multiple times, as received signals by switching between a plurality of antennas of the network device during reception of each occurrence of the response packet. The received signals are converted to corrupted orthogonal samples. The response packet is received from the station device a final time as a final response packet via a single antenna of the plurality of antennas. Ideal orthogonal samples are re-generated based at least in part on the final response packet. Signal phase information, embedded in the corrupted and ideal orthogonal samples, is converted into estimated locations of the station device.
Abstract:
The present disclosure describes methods and apparatuses for implementing virtual dynamic library loading in embedded systems. In some aspects, a determination is made that a feature is not available in firmware executed from a first memory. Based on information associated with the feature, a portion of a second memory is allocated for code of the feature. In some cases, the portion of the second memory is allocated from a data buffer or part of a shared memory. The code of the feature is loaded to the allocated portion of the second memory and address aliasing logic is configured enable execution of the feature from the second memory. By allocating and executing firmware features from the second memory, a size of the firmware executed from the first memory can be reduced to conserve memory space and other firmware features may be dynamically loaded and executed from the second memory.
Abstract:
An example embodiment includes an apparatus. The apparatus includes piconet logic for establishing a multi-level piconet hierarchy having a top level piconet and a lower level piconet(s). The top level piconet includes a master device and master controller(s). The lower level piconet includes master controllers(s) and sub-controller(s). The apparatus includes time division multiplexing logic to solicit and control aggregated communication with master controllers. The aggregated communication comprises data from the master controller and data from a sub-controller(s).