公开(公告)号：US11611334B2

公开(公告)日：2023-03-21

申请号：US17504485

申请日：2021-10-18

Applicant: MEDIATEK INC.

Inventor： Shou-En Liu ,  Wen-Sung Chiang ,  Ming-Han Hsieh ,  Keng-Jui Chang ,  Lin-Chien Chen

IPC: H03K3/017 ,  H03M13/25 ,  G06F1/08

Abstract: A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

公开(公告)号：US20220357211A1

公开(公告)日：2022-11-10

申请号：US17719387

申请日：2022-04-13

Applicant: MEDIATEK INC.

Inventor： Min-Hang Hsieh ,  Jyun-Jia Huang ,  Chien-Sheng Chao ,  Ghien-An Shih ,  Ching-Chung Ko ,  Yu-Cheng Su ,  Lin-Chien Chen ,  Ai-Yun Liu ,  Chia-Hsin Hu

IPC: G01K7/01

Abstract: The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.

公开(公告)号：US20220166412A1

公开(公告)日：2022-05-26

申请号：US17504485

申请日：2021-10-18

Applicant: MEDIATEK INC.

Inventor： Shou-En Liu ,  Wen-Sung Chiang ,  Ming-Han Hsieh ,  Keng-Jui Chang ,  Lin-Chien Chen

IPC: H03K3/017 ,  G06F1/08 ,  H03M13/25

Abstract: A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.