公开(公告)号：US20240211673A1

公开(公告)日：2024-06-27

申请号：US18522162

申请日：2023-11-28

Applicant: Mediatek INC.

Inventor： Pang-Yen Chin ,  Yu-Sian Lin ,  Ri-Cheng Zeng ,  Chi-Shun Cheng ,  Wei-Hsin Tseng ,  Kuan-Ta Chen ,  Chia-Hsin Hu

IPC: G06F30/392 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L27/0207 ,  G06F2111/20

Abstract: A method for designing an integrated circuit layout includes: generating an analog standard cell library and designing the integrated circuit layout by using at least the analog standard cell library, where the step of generating the analog standard cell library includes creating a target analog standard cell that is included in the analog standard cell library and does not violate layout rules of digital standard cells. Another method for designing an integrated circuit layout includes: generating a mixed-signal standard cell library and designing the integrated circuit layout by using at least the mixed-signal standard cell library, where the step of generating the mixed-signal standard cell library includes creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells.

公开(公告)号：US20240379549A1

公开(公告)日：2024-11-14

申请号：US18638650

申请日：2024-04-17

Applicant: MEDIATEK INC.

Inventor： Shih-Chuan Chiu ,  Chia-Hsin Hu ,  Zheng Zeng

IPC: H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/861

Abstract: The present invention provides a semiconductor structure, wherein the semiconductor structure includes an oxide definition region, a plurality of metal gate structures and a plurality of S/D contacts. The oxide definition region is disposed over a semiconductor substrate and surrounded by insulating regions. The plurality of metal gate structures are disposed on an N-well or a P-well manufactured on the semiconductor substrate. The plurality of S/D contacts are disposed on the N-well or the P-well manufactured on the semiconductor substrate. In addition, the plurality of metal gate structures, the plurality of S/D contacts and the at least one dummy gate structure are within the oxide definition region.

公开(公告)号：US20220357211A1

公开(公告)日：2022-11-10

申请号：US17719387

申请日：2022-04-13

Applicant: MEDIATEK INC.

Inventor： Min-Hang Hsieh ,  Jyun-Jia Huang ,  Chien-Sheng Chao ,  Ghien-An Shih ,  Ching-Chung Ko ,  Yu-Cheng Su ,  Lin-Chien Chen ,  Ai-Yun Liu ,  Chia-Hsin Hu

IPC: G01K7/01

Abstract: The present invention provides a processing circuit including logic cells and a thermal sensor. The thermal sensor is positioned within the logic cells and surrounded by the logic cells, and the logic cells and the thermal sensor are all implemented by core devices.