公开(公告)号：US11715754B2

公开(公告)日：2023-08-01

申请号：US17319078

申请日：2021-05-12

Applicant: MEDIATEK INC.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L23/48 ,  H01L49/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2924/1436 ,  H01L2924/182 ,  H01L2924/19042

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US09972673B2

公开(公告)日：2018-05-15

申请号：US15469846

申请日：2017-03-27

Applicant: MediaTek Inc.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Bo-Shih Huang

IPC: H01L23/62 ,  H01L29/06 ,  H01L27/02 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/0619 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

公开(公告)号：US20140127869A1

公开(公告)日：2014-05-08

申请号：US14161570

申请日：2014-01-22

Applicant: MEDIATEK INC.

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

公开(公告)号：US10002833B2

公开(公告)日：2018-06-19

申请号：US15604924

申请日：2017-05-25

Applicant: MediaTek Inc.

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC: H01L27/10 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

公开(公告)号：US09698102B2

公开(公告)日：2017-07-04

申请号：US15168519

申请日：2016-05-31

Applicant: MediaTek Inc.

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC: H01L27/10 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

公开(公告)号：US09324705B2

公开(公告)日：2016-04-26

申请号：US14161611

申请日：2014-01-22

Applicant: MEDIATEK INC.

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L29/735 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。

公开(公告)号：US20240079444A1

公开(公告)日：2024-03-07

申请号：US18332863

申请日：2023-06-12

Applicant: MediaTek Inc.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2924/1436 ,  H01L2924/182 ,  H01L2924/19042

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US20170263559A1

公开(公告)日：2017-09-14

申请号：US15604924

申请日：2017-05-25

Applicant: MediaTek Inc.

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

公开(公告)号：US20210384291A1

公开(公告)日：2021-12-09

申请号：US17319078

申请日：2021-05-12

Applicant: MEDIATEK INC.

Inventor： Zheng Zeng ,  Ching-Chung Ko ,  Kuei-Ti Chan

IPC: H01L49/02 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

公开(公告)号：US08836043B2

公开(公告)日：2014-09-16

申请号：US14161570

申请日：2014-01-22

Applicant: Mediatek Inc.

Inventor： Ching-Chung Ko ,  Tung-Hsing Lee

IPC: H01L29/739 ,  H01L21/8249 ,  H01L29/735 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.

Abstract translation: 横向双极结晶体管包括发射极区域; 围绕发射极区域的基极区域; 设置在所述基部区域的至少一部分上的栅极; 以及围绕所述基底区域的收集器区域; 其中所述栅极下方的所述基极区域的所述部分未经过阈值电压注入工艺。