公开(公告)号：US20230014046A1

公开(公告)日：2023-01-19

申请号：US17848417

申请日：2022-06-24

Applicant: MEDIATEK INC.

Inventor： Ruey-Bo Sun ,  Sheng-Mou Lin

IPC: H01L23/552

Abstract: According to an embodiment of the invention, a semiconductor device comprises a substrate, a semiconductor die and a first shielding structure. The semiconductor die is disposed on the substrate and comprises an electronic device. The first shielding structure is formed outside of the semiconductor die and disposed under the electronic device.

公开(公告)号：US20240038690A1

公开(公告)日：2024-02-01

申请号：US18211551

申请日：2023-06-19

Applicant: MEDIATEK INC.

Inventor： Po-Jui Li ,  Ruey-Bo Sun ,  Yen-Ju Lu ,  Chun-Yuan Yeh ,  Sheng-Mou Lin

IPC: H01L23/64 ,  H01L23/522

CPC classification number: H01L23/645 ,  H01L23/5227 ,  H01L23/5221 ,  H01L28/10

Abstract: A semiconductor device includes an electronic device, a guard trace and a first trace. The guard trace is connecting to a ground layer through a first ground via. The first trace is disposed adjacent to the electronic device and the guard trace and includes a first segment. A phase or a direction of a first current signal conducted on the first trace is changed in the first segment. The electronic device and the first trace are disposed at different sides of the guard trace and the first ground via is beside the first segment.

公开(公告)号：US10446508B2

公开(公告)日：2019-10-15

申请号：US15682908

申请日：2017-08-22

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou Lin ,  Chih-Chun Hsu ,  Wen-Chou Wu

IPC: H01L23/66 ,  H01L23/64 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

公开(公告)号：US20200058633A1

公开(公告)日：2020-02-20

申请号：US16535019

申请日：2019-08-07

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou Lin ,  Wen-Chou Wu ,  Hsing-Chih Liu

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552

Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

公开(公告)号：US20200051927A1

公开(公告)日：2020-02-13

申请号：US16539808

申请日：2019-08-13

Applicant: MediaTek Inc.

Inventor： Yi-Chieh Lin ,  Sheng-Mou Lin ,  Wen-Chou Wu

IPC: H01L23/552 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device includes a first layer structure, a first layer structure, a second layer structure and a passive electronic component. The second layer structure is disposed below the first layer structure and coupled to a ground. The conductive structure is coupled to the first layer structure. The conductive structure is installed vertically between the first layer structure and the second layer structure, and is coupled to a first pad of the second layer structure. The passive electronic component comprises a first terminal coupled to the first pad of the second layer structure and a second terminal coupled to a second pad of the second layer structure. The conductive structure and the passive electronic component are connected in series between the first layer structure and the ground to form a conductive path for conducting at least one electromagnetic interference signal to the ground.

公开(公告)号：US10340235B2

公开(公告)日：2019-07-02

申请号：US15841667

申请日：2017-12-14

Applicant: MEDIATEK INC.

Inventor： Chih-Chun Hsu ,  Sheng-Mou Lin

IPC: H01L27/08 ,  H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.

公开(公告)号：US10068857B2

公开(公告)日：2018-09-04

申请号：US15794128

申请日：2017-10-26

Applicant: MEDIATEK INC.

Inventor： Ruey-Bo Sun ,  Sheng-Mou Lin ,  Wen-Chou Wu

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/495 ,  H01L49/02 ,  H01L23/522

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate, a semiconductor die, a base and a first inductor structure. The substrate has a die-attach surface and a solder-ball-attach surface opposite to the die-attach surface. The semiconductor die is mounted on the die-attach surface of the substrate. The semiconductor die includes a radio-frequency (RF) circuit and a first RF die pad electrically connected to the RF circuit. The base is mounted on the solder-ball-attach surface of the substrate. The first inductor structure is positioned on the substrate, the semiconductor die or the base. The first inductor structure includes a first terminal electrically connected to the first die pad and a second terminal electrically connected to a ground terminal.

公开(公告)号：US12062864B2

公开(公告)日：2024-08-13

申请号：US18233335

申请日：2023-08-14

Applicant: MEDIATEK INC.

Inventor： Debapratim Dhara ,  Shih-Chia Chiu ,  Yen-Ju Lu ,  Sheng-Mou Lin

IPC: H01Q9/04 ,  H01Q1/48

CPC classification number: H01Q9/045 ,  H01Q1/48

Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.

公开(公告)号：US11764475B2

公开(公告)日：2023-09-19

申请号：US17411038

申请日：2021-08-24

Applicant: MEDIATEK INC.

Inventor： Debapratim Dhara ,  Shih-Chia Chiu ,  Yen-Ju Lu ,  Sheng-Mou Lin

IPC: H01Q1/48 ,  H01Q9/04

CPC classification number: H01Q9/045 ,  H01Q1/48

Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.

公开(公告)号：US20220102859A1

公开(公告)日：2022-03-31

申请号：US17411038

申请日：2021-08-24

Applicant: MEDIATEK INC.

Inventor： Debapratim Dhara ,  Shih-Chia Chiu ,  Yen-Ju Lu ,  Sheng-Mou Lin

IPC: H01Q9/04 ,  H01Q1/48

Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.