公开(公告)号：US09977699B2

公开(公告)日：2018-05-22

申请号：US14936686

申请日：2015-11-10

Applicant: MediaTek Inc.

Inventor： Jia-Ming Chen ,  Hung-Lin Chou ,  Ya-Ting Chang ,  Shih-Yen Chiu ,  Chia-Hao Hsu ,  Yu-Ming Lin ,  Wan-Ching Huang ,  Jen-Chieh Yang ,  Pi-Cheng Hsiao

IPC: G06F9/46 ,  G06F9/50 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/329 ,  G06F2209/505 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

公开(公告)号：US20160062447A1

公开(公告)日：2016-03-03

申请号：US14811851

申请日：2015-07-29

Applicant: Mediatek Inc.

Inventor： Jih-Ming Hsu ,  Wen-Tsan Hsieh ,  Che-Ming Hsu ,  Yeh-Ji Chou ,  Jen-Chieh Yang ,  Shih-Yen Chiu ,  Wan-Ching Huang ,  Ming-Hsien Lee

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.

Abstract translation: 提供了一种用于动态管理计算系统的多核处理器的功率的方法和计算机可读介质。 多核处理器生成动态电压和频率缩放（DVFS）表，通过交替地选择功率预算或其所需性能来确定第一索引，确定计算系统的当前线程级并行度（TLP），选择一个 根据当前TLP和第一索引的条目，并且根据所选择的条目的第一设置和第二设置来配置第一核心和第二核心。

公开(公告)号：US09665161B2

公开(公告)日：2017-05-30

申请号：US14811851

申请日：2015-07-29

Applicant: MEDIATEK INC.

Inventor： Jih-Ming Hsu ,  Wen-Tsan Hsieh ,  Che-Ming Hsu ,  Yeh-Ji Chou ,  Jen-Chieh Yang ,  Shih-Yen Chiu ,  Wan-Ching Huang ,  Ming-Hsien Lee

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.

公开(公告)号：US20170160962A1

公开(公告)日：2017-06-08

申请号：US15363181

申请日：2016-11-29

Applicant: MediaTek Inc.

Inventor： Shih-Yen Chiu ,  Wan-Ching Huang ,  Chung-Ho Chang ,  Ya-Ting Chang ,  Ming-Ju Wu ,  Nicholas Ching Hui Tang

IPC: G06F3/06

CPC classification number: G06F9/5077 ,  G06F9/455

Abstract: A multicore processor system includes multiple processor cores. When a processor core goes offline, the offline processor core is mapped to a mapped processor core, which is selected from an emulated processor core and one or more online processor cores among the multiple processor cores. The emulated processor core is a software construct containing an emulated state of the offline processor core. When the multicore processor system receives a system call that is sent from a requestor to the offline processor core to request for system information from the offline processor core, the system call is re-directed to the mapped processor core. The system information is returned from the mapped processor core to the requestor in response to the system call.