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公开(公告)号：US20230004392A1
公开(公告)日：2023-01-05
申请号：US17367367
申请日：2021-07-04
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Zachy Haramaty , Yaniv Strassberg , Itsik Levi , Alon Singer
Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.
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公开(公告)号：US11681635B2
公开(公告)日：2023-06-20
申请号：US17013693
申请日：2020-09-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Yuval Itkin , Yaniv Strassberg , Guy Harel , Ahmad Atamlh
IPC: G06F12/14 , G06F21/79 , G06F12/02 , G06F12/0891
CPC classification number: G06F12/1408 , G06F12/0246 , G06F12/0891 , G06F21/79
Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.
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公开(公告)号：US12216580B1
公开(公告)日：2025-02-04
申请号：US18456536
申请日：2023-08-28
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Yaniv Strassberg , Guy Harel , Gabi Liron , Yuval Itkin
IPC: G06F12/08 , G06F12/0815 , G06F12/084 , G06F12/14
Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.
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公开(公告)号：US20240370579A1
公开(公告)日：2024-11-07
申请号：US18142968
申请日：2023-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan Finkelshtein , Michael Tahar , Irit Granovsky , Yaniv Strassberg , Guy-Avraham Harel
Abstract: A system, circuit, and method are described, among other things. An illustrative system is disclosed to include a processor and a memory storing data for processing by the processor. The data, when processed, causes the processor to receive an initiator message comprising a request to access one or more registers of a plurality of registers, determine that the initiator message corresponds to an entry of a privilege access table, determine a configured level of access control for the initiator message to access the one or more requested registers based at least in part on a group mapping table, and provide a level of access to the one or more requested registers corresponding to the received initiator message based on the initiator message corresponding to the entry of the privilege access table and based, at least in part, on the determined configured level of access control.
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公开(公告)号：US11741232B2
公开(公告)日：2023-08-29
申请号：US17163599
申请日：2021-02-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Mor Hoyda Sfadia , Yuval Itkin , Ahmad Atamli , Ariel Shahar , Yaniv Strassberg , Itsik Levi
CPC classification number: G06F21/572 , G06F8/65 , G06F9/445 , G06F2221/033
Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
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Patent Agency Ranking
公开(公告)号：US20250077429A1
公开(公告)日：2025-03-06
申请号：US18950269
申请日：2024-11-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Yaniv Strassberg , Guy Harel , Gabi Liron , Yuval Itkin
IPC: G06F12/0815 , G06F12/084 , G06F12/14
Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.
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公开(公告)号：US12223051B2
公开(公告)日：2025-02-11
申请号：US18349147
申请日：2023-07-09
Applicant: Mellanox Technologies, Ltd.
Inventor： Mor Hoyda Sfadia , Yuval Itkin , Ahmad Atamli , Ariel Shahar , Yaniv Strassberg , Itsik Levi
Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
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公开(公告)号：US20230351021A1
公开(公告)日：2023-11-02
申请号：US18349147
申请日：2023-07-09
Applicant: Mellanox Technologies, Ltd.
Inventor： Mor Hoyda Sfadia , Yuval Itkin , Ahmad Atamli , Ariel Shahar , Yaniv Strassberg , Itsik Levi
CPC classification number: G06F21/572 , G06F8/65 , G06F9/445 , G06F2221/033
Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
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公开(公告)号：US11734005B2
公开(公告)日：2023-08-22
申请号：US17367367
申请日：2021-07-04
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Zachy Haramaty , Yaniv Strassberg , Itsik Levi , Alon Singer
CPC classification number: G06F9/30101 , G06F12/023 , G06F2212/251
Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.
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公开(公告)号：US20220245251A1
公开(公告)日：2022-08-04
申请号：US17163599
申请日：2021-02-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Mor Hoyda Sfadia , Yuval Itkin , Ahmad Atamli , Ariel Shahar , Yaniv Strassberg , Itsik Levi
Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
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