公开(公告)号：US20140115206A1

公开(公告)日：2014-04-24

申请号：US13658976

申请日：2012-10-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Oren Tzvi Sela ,  Noam Bloch

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/423 ,  G06F2213/0026

Abstract: Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol.

Abstract translation: 披露了通过Peripheral Component Interconnect Express运行网络协议的方法和设备。 方法和装置可以接收包括数据的电子信号。 方法和设备还可以确定对应于从包括PCIe协议和网络协议的集合中选择的协议的数据。 此外，方法和设备还可以基于所确定的协议来配置CPU。 所述方法和设备还可以接收包括在CPU的引脚或引脚上的第二数据的第二电子信号，其中所述引脚或引脚连接到PCIe通道，并且其中根据所确定的协议对第二数据进行格式化。 此外，方法和装置可以根据确定的协议处理第二数据。

公开(公告)号：US08990472B2

公开(公告)日：2015-03-24

申请号：US13658976

申请日：2012-10-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Oren Tzvi Sela ,  Noam Bloch

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/423 ,  G06F2213/0026

Abstract: Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol.

Abstract translation: 披露了通过Peripheral Component Interconnect Express运行网络协议的方法和设备。 方法和装置可以接收包括数据的电子信号。 方法和设备还可以确定对应于从包括PCIe协议和网络协议的集合中选择的协议的数据。 此外，方法和设备还可以基于所确定的协议来配置CPU。 所述方法和设备还可以接收包括在CPU的引脚或引脚上的第二数据的第二电子信号，其中所述引脚或引脚连接到PCIe通道，并且其中根据所确定的协议对第二数据进行格式化。 此外，方法和装置可以根据确定的协议处理第二数据。

公开(公告)号：US20140281840A1

公开(公告)日：2014-09-18

申请号：US13839193

申请日：2013-03-15

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Liron Mula ,  Ran Ravid ,  Chen Gaist ,  Omer Sela ,  Oren Tzvi Sela

IPC: H03M13/15

CPC classification number: H03M13/1515 ,  H03M13/153 ,  H03M13/1575 ,  H03M13/3715

Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.

Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。

公开(公告)号：US09344117B2

公开(公告)日：2016-05-17

申请号：US13839193

申请日：2013-03-15

Applicant: Mellanox Technologies Ltd.

Inventor： Liron Mula ,  Ran Ravid ,  Chen Gaist ,  Omer Sella ,  Oren Tzvi Sela

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/37

CPC classification number: H03M13/1515 ,  H03M13/153 ,  H03M13/1575 ,  H03M13/3715

Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.

Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。