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    Caching Policy In A Multicore System On A Chip (SOC)
    1.
    发明申请
    Caching Policy In A Multicore System On A Chip (SOC) 审中-公开

    公开(公告)号：US20180349292A1

    公开(公告)日：2018-12-06

    申请号：US15610823

    申请日：2017-06-01

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Gilad Tal ,  Gil Moran ,  Miriam Menes ,  Gil Kopilov ,  Shlomo Raikin

    IPC: G06F12/123 ,  G06F12/0808

    Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected access profile from plural access profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected access profile for a selected least recently used (LRU) position in the cache.

    Address translation services for direct accessing of local memory over a network fabric
    2.
    发明授权
    Address translation services for direct accessing of local memory over a network fabric 有权

    公开(公告)号：US10031857B2

    公开(公告)日：2018-07-24

    申请号：US14953462

    申请日：2015-11-30

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Adi Menachem ,  Shlomo Raikin ,  Idan Burstein ,  Michael Kagan

    IPC: G06F13/36 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/38 ,  G06F13/28

    Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.

    DIRECT ACCESS TO LOCAL MEMORY IN A PCI-E DEVICE
    6.
    发明申请
    DIRECT ACCESS TO LOCAL MEMORY IN A PCI-E DEVICE 审中-公开
    直接访问PCI-E设备中的本地存储器

    公开(公告)号：US20150347349A1

    公开(公告)日：2015-12-03

    申请号：US14721009

    申请日：2015-05-26

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Shachar Raindel ,  Idan Burstein ,  Noam Bloch ,  Shlomo Raikin

    IPC: G06F15/173 ,  G06F13/42 ,  G06F13/28

    CPC classification number: G06F15/17331 ,  G06F13/28 ,  G06F13/4221

    Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.

    Abstract translation: 一种方法包括根据总线地址空间通过总线在至少第一和第二设备之间进行通信，包括通过映射本地地址的至少一些地址来提供总线上的直接访问到第一设备的本地地址空间 空间到公交地址空间。 响应于由第一设备或第二设备指示第二设备需要访问当前未映射到总线地址空间的本地地址空间中的本地地址，将本地地址映射到总线地址空间 ，并且第二设备使用映射直接访问本地地址。

    ACCESSING REMOTE STORAGE DEVICES USING A LOCAL BUS PROTOCOL
    7.
    发明申请
    ACCESSING REMOTE STORAGE DEVICES USING A LOCAL BUS PROTOCOL 有权
    使用本地总线协议访问远程存储设备

    公开(公告)号：US20150261720A1

    公开(公告)日：2015-09-17

    申请号：US14215097

    申请日：2014-03-17

    Applicant: Mellanox Technologies Ltd.

    Inventor： Michael Kagan ,  Noam Bloch ,  Shlomo Raikin ,  Yaron Haviv ,  Idan Burstein

    IPC: G06F15/173 ,  G06F13/28 ,  G06F3/06 ,  G06F13/42

    CPC classification number: G06F3/0659 ,  G06F13/287 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method for data storage includes configuring a driver program on a host computer to receive commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer. When the driver program receives, from an application program running on the host computer a storage access command in accordance with the protocol, specifying a storage transaction, a remote direct memory access (RDMA) operation is performed by a network interface controller (NIC) connected to the host computer so as to execute the storage transaction via a network on a remote storage device.

    Abstract translation: 一种用于数据存储的方法包括：在主计算机上配置驱动程序，以根据为访问连接到主计算机的外围组件接口总线的本地存储设备而定义的协议接收命令。 当驱动程序从主计算机上运行的应用程序接收到根据协议的存储访问命令指定存储事务时，由连接的网络接口控制器（NIC）执行远程直接存储器访问（RDMA）操作 到主计算机，以便经由远程存储设备上的网络执行存储交易。

    EFFICIENT MANAGEMENT OF NETWORK TRAFFIC IN A MULTI-CPU SERVER
    8.
    发明申请
    EFFICIENT MANAGEMENT OF NETWORK TRAFFIC IN A MULTI-CPU SERVER 审中-公开
    多CPU服务器中网络流量的有效管理

    公开(公告)号：US20150222547A1

    公开(公告)日：2015-08-06

    申请号：US14608265

    申请日：2015-01-29

    Applicant: Mellanox Technologies Ltd.

    Inventor： Ofer Hayut ,  Noam Bloch ,  Shlomo Raikin ,  Liran Liss

    IPC: H04L12/803 ,  H04L12/721

    CPC classification number: H04L49/00

    Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

    Abstract translation: 网络接口控制器（NIC）包括网络接口，对等接口和转向逻辑。 网络接口被配置为从通信网络接收传入的分组。 对等体接口被配置为不通过通信网络与对等网络进行通信。 转向逻辑被配置为将通过网络接口接收的分组分类为目的地由NIC服务的本地中央处理单元（CPU）的第一入局分组，以及指向由对等体服务的远程CPU的第二传入分组 NIC，将首次传入的数据包转发到本地CPU，并通过对等接口将第二个传入数据包转发到对等网络，而不是通过通信网络。

    Host bus access by add-on devices via a network interface controller
    9.
    发明授权
    Host bus access by add-on devices via a network interface controller 有权

    公开(公告)号：US10152441B2

    公开(公告)日：2018-12-11

    申请号：US15154945

    申请日：2016-05-14

    Applicant: Mellanox Technologies Ltd.

    Inventor： Liran Liss ,  Shachar Raindel ,  Shlomo Raikin ,  Adi Menachem ,  Yuval Itkin

    IPC: G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  G06F13/28 ,  H04L12/861 ,  G06F13/40 ,  H04L12/935

    Abstract: Peripheral apparatus for use with a host computer includes an add-on device, which includes a first network port coupled to one end of a packet communication link and add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data. A network interface controller (NIC) includes a host bus interface, configured for connection to the host bus of the host computer and a second network port, coupled to the other end of the packet communication link. Packet processing logic in the NIC is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the resources of the host computer.

    Network-based computational accelerator
    10.
    发明授权
    Network-based computational accelerator 有权

    公开(公告)号：US10135739B2

    公开(公告)日：2018-11-20

    申请号：US15145983

    申请日：2016-05-04

    Applicant: Mellanox Technologies Ltd.

    Inventor： Shachar Raindel ,  Shlomo Raikin ,  Liran Liss

    IPC: H04L29/06 ,  H04L12/801 ,  H04L29/08 ,  G06F21/60 ,  H04L12/851

    Abstract: A data processing device includes a first packet communication interface for communication with at least one host processor via a network interface controller (NIC) and a second packet communication interface for communication with a packet data network. A memory holds a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second interfaces packet communication interfaces. Acceleration logic, coupled between the first and second packet communication interfaces, performs computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

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