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    Configurable time delays for equalizing pulse width modulation timing
    1.
    发明授权
    Configurable time delays for equalizing pulse width modulation timing 有权
    用于均衡脉宽调制时序的可组态时间延迟

    公开(公告)号：US08866525B2

    公开(公告)日：2014-10-21

    申请号：US13778436

    申请日：2013-02-27

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  John Day ,  Alex Dumais ,  Stephen Bowling

    IPC: H03K3/017 ,  H03K5/13

    CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

    Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

    System with Increasing Protected Storage Area and Erase Protection
    2.
    发明申请
    System with Increasing Protected Storage Area and Erase Protection 有权

    公开(公告)号：US20220113879A1

    公开(公告)日：2022-04-14

    申请号：US17499167

    申请日：2021-10-12

    Applicant: Microchip Technology Incorporated

    Inventor： Roshan Samuel ,  Erick Pfeifer ,  John Day ,  Daniel Ujvari

    IPC: G06F3/06

    Abstract: An apparatus may include a processor. The apparatus may include a memory communicatively coupled to the processor. The apparatus may include a memory control circuit (MCC). The MCC may be configured to define a protected portion of the memory, wherein the protected portion of the memory is configured for read-only access by the processor, increase a size of the protected portion of the memory, and, after the increase in size of the protected portion of the memory, prevent decreases of the size of the protected portion of the memory.

    SYSTEM AND METHODS FOR RAMP CONTROL
    3.
    发明公开
    SYSTEM AND METHODS FOR RAMP CONTROL 审中-公开

    公开(公告)号：US20240022257A1

    公开(公告)日：2024-01-18

    申请号：US18095933

    申请日：2023-01-11

    Applicant: Microchip Technology Incorporated

    Inventor： Andreas Reiter ,  Yong Yuenyongsgool ,  Stephen Bowling ,  John Day ,  Alex Dumais ,  Justin Oshea

    IPC: H03M1/56

    CPC classification number: H03M1/56

    Abstract: A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.

    CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING
    5.
    发明申请
    CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING 有权
    用于均衡脉冲宽度调制时序的可配置时间延迟

    公开(公告)号：US20140240020A1

    公开(公告)日：2014-08-28

    申请号：US13778436

    申请日：2013-02-27

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Bryan Kris ,  John Day ,  Alex Dumais ,  Stephen Bowling

    IPC: H03K5/13

    CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

    Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

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