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    TEMPERATURE COMPENSATED CLOCK FREQUENCY MONITOR
    3.
    发明申请
    TEMPERATURE COMPENSATED CLOCK FREQUENCY MONITOR 审中-公开

    公开(公告)号：US20190094905A1

    公开(公告)日：2019-03-28

    申请号：US16143967

    申请日：2018-09-27

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  Igor Wojewoda ,  Stephen Bowling ,  Yong Yuenyongsgool

    IPC: G06F1/08 ,  G06F1/20 ,  G06F11/30 ,  G01R23/15 ,  G01R19/25 ,  G05B13/02

    Abstract: A temperature-compensating clock frequency monitor circuit may be provided to detect a clock pulse frequency in an electronic device that may cause erratic or dangerous operation of the device, as a function of an operating temperature of the device. The temperature-compensating clock frequency monitor circuit include a temperature sensor configured to measure a temperature associated with an electronic device, a clock having an operating frequency, and a frequency monitoring system. The frequency monitoring system may be configured to determine the operating frequency of the clock, and based at least on (a) the operating frequency of the clock and (b) the measured temperature associated with the electronic device, generate a corrective action signal to initiate a corrective action associated with the electronic device or a related device. The temperature sensor, clock, and frequency monitoring system may, for example, be provided on a microcontroller.

    Time-based delay line analog comparator
    4.
    发明授权
    Time-based delay line analog comparator 有权

    公开(公告)号：US10003353B2

    公开(公告)日：2018-06-19

    申请号：US15652710

    申请日：2017-07-18

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  Jim Bartling ,  Neil Deutscher

    IPC: H03M1/12 ,  H03M1/50 ,  H03K5/14 ,  H03K5/24

    CPC classification number: H03M1/502 ,  H03K5/14 ,  H03K5/24 ,  H03M1/1205

    Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.

    COMBINATORIAL/SEQUENTIAL PULSE WIDTH MODULATION
    5.
    发明申请
    COMBINATORIAL/SEQUENTIAL PULSE WIDTH MODULATION 审中-公开
    组合/顺序脉冲宽度调制

    公开(公告)号：US20160269016A1

    公开(公告)日：2016-09-15

    申请号：US15064843

    申请日：2016-03-09

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  Stephen Bowling ,  Alex Dumais

    IPC: H03K7/08 ,  H02M1/08

    CPC classification number: H03K7/08 ,  H02M1/08 ,  H02M3/157 ,  H02M2001/0012

    Abstract: A number of standard PWM generators produce PWM signals that may be used to drive the power stages for Full-Bridge, Feed-Forward, Push-Pull, Phase-Shift Zero Voltage Transition (ZVT), and other switched mode power supply (SMPS) conversion topologies. These PWM signals may be fed to logic functions of a combinatorial logic block. Appropriate PWM signals are selected as operands along with desired logic function(s) that operates on these input operands. The resultant combinatorial PWM signals may then be used directly or may be fed through dead-time processing circuitry prior to outputting to an application circuit. In addition to the combinatorial logic functions, sequential logic functions may also be used to provide sequential PWM signals, e.g., synchronous sequential, asynchronous sequential, and/or sequential-combinatorial PWM signals.

    Abstract translation: 许多标准PWM发生器产生可用于驱动全桥，前馈，推挽，相移零电压转换（ZVT）和其他开关模式电源（SMPS）的功率级的PWM信号， 转换拓扑。 这些PWM信号可以被馈送到组合逻辑块的逻辑功能。 选择适当的PWM信号作为操作数以及对这些输入操作数进行操作的所需逻辑功能。 所得到的组合PWM信号可以直接使用，或者可以在输出到应用电路之前通过死区时间处理电路馈送。 除了组合逻辑功能之外，顺序逻辑功能还可用于提供顺序PWM信号，例如同步顺序，异步顺序和/或顺序组合PWM信号。

    Low-Pin Microcontroller Device With Multiple Independent Microcontrollers
    6.
    发明申请
    Low-Pin Microcontroller Device With Multiple Independent Microcontrollers 有权
    具有多个独立微控制器的低引脚微控制器器件

    公开(公告)号：US20160267047A1

    公开(公告)日：2016-09-15

    申请号：US15065027

    申请日：2016-03-09

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  Igor Wojewoda ,  Alex Dumais ,  Mike Catherwood ,  Brian Fall ,  Jason Tollefson ,  Calum Wilke ,  Dave Mickey ,  Thomas Spohrer ,  Jim Pepping ,  Vincent Sheard

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/364

    CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

    Abstract translation: 微控制器装置具有壳体，其具有多个外部引脚，第一微控制器具有第一中央处理单元（CPU），与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器和第一多个外设 与第一系统总线耦合的设备，以及具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备 第二系统总线，其中第一和第二微控制器仅通过专用接口进行通信。

    PULSE DENSITY MODULATION DIGITAL-TO-ANALOG CONVERTER WITH TRIANGLE WAVE GENERATION
    7.
    发明申请
    PULSE DENSITY MODULATION DIGITAL-TO-ANALOG CONVERTER WITH TRIANGLE WAVE GENERATION 有权
    脉冲密度调制数字到模拟转换器，具有三角波生成

    公开(公告)号：US20160134295A1

    公开(公告)日：2016-05-12

    申请号：US14538036

    申请日：2014-11-11

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris

    IPC: H03M1/06 ,  H03M1/66 ,  H03K4/06

    CPC classification number: H03K4/06 ,  G06F1/022 ,  H03K7/08 ,  H03M1/0631 ,  H03M1/825

    Abstract: A phase accumulator style circuit generates an output stream of pulses. The density of the pulse stream is proportional to the input data value relative to the maximum value supported by the bit width of an adder. The output pulse density is representative of the desired output voltage. The pulse stream may be filtered with a resistor-capacitor (RC) low pass filter to yield an analog voltage. Faster clock rates support the use of smaller output filters that reduce circuit cost. This circuit provides triangle wave generation wherein the DAC output ramps up and down at a user specified rate (slope) between user specified maximum and minimum amplitude values. The up and down triangle wave ramp rates (up and down slopes) may be different and independent or the same.

    Abstract translation: 相位累加器式电路产生输出脉冲流。 脉冲流的密度与输入数据值相对于由加法器的位宽度支持的最大值成比例。 输出脉冲密度代表所需的输出电压。 可以用电阻 - 电容（RC）低通滤波器对脉冲流进行滤波，以产生模拟电压。 更快的时钟速率支持使用更小的输出滤波器，降低电路成本。 该电路提供三角波生成，其中DAC输出以用户指定的最大和最小振幅值之间的用户指定速率（斜率）上下翻转。 上下三角波斜坡速率（上下斜坡）可能是不同的和独立的或相同的。

    Pulse width modulation load share bus
    8.
    发明授权
    Pulse width modulation load share bus 有权
    脉宽调制负载共享总线

    公开(公告)号：US09106136B2

    公开(公告)日：2015-08-11

    申请号：US13764423

    申请日：2013-02-11

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris

    IPC: G06F1/00 ,  H02M3/158 ,  H02J1/10 ,  G06F1/26

    CPC classification number: H02M3/1584 ,  G06F1/263 ,  H02J1/102

    Abstract: Power supply modules have outputs coupled in parallel and convey load share balancing information over a single wire load share bus. Pulse width modulation (PWM) signals represent output loading of each of the power supply modules over the single wire load share bus. The PWM load share signal width (time asserted) of the PWM signal represents the output loading of the respective power supply module. Each of the power supply modules detect the assertion of the PWM signal on the load share bus and then each of them simultaneously drive the load share bus with a PWM signal representing their respective output loading. The power supply module having the greatest percent loading will assert its PWM load share signal longest, and the other power supply modules will thereafter adjust their outputs to more evenly supply power outputs to the load.

    Abstract translation: 电源模块具有并联耦合的输出，并通过单个有线负载共享总线传送负载共享平衡信息。 脉宽调制（PWM）信号表示单线负载共享总线上每个电源模块的输出负载。 PWM信号的PWM负载共享信号宽度（时间有效）表示相应电源模块的输出负载。 每个电源模块检测负载共享总线上的PWM信号的断言，然后它们每个都以表示其相应输出负载的PWM信号同时驱动负载共享总线。 具有最大负载百分比的电源模块将使其PWM负载共享信号最长，其他电源模块此后会调整其输出以更均匀地向负载提供电源输出。

    Variable frequency ratiometric multiphase pulse width modulation generation
    9.
    发明授权
    Variable frequency ratiometric multiphase pulse width modulation generation 有权
    可变频率比较多相脉宽调制生成

    公开(公告)号：US08878581B2

    公开(公告)日：2014-11-04

    申请号：US14165222

    申请日：2014-01-27

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris

    IPC: H03K3/017 ,  G06F1/04 ,  H03K7/08 ,  G06F1/26

    CPC classification number: H03K7/08 ,  G06F1/04 ,  G06F1/26

    Abstract: Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

    Abstract translation: 产生相移脉冲宽度调制信号组，其维持其占空比和相位关系作为PWM信号频率周期的函数。 以比例度量方式生成多相PWM信号，以便大大简化并减少PWM系统中使用的处理器的计算工作量。 相移PWM信号组也可以与外部同步信号同步并自动缩放。

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