公开(公告)号：US20230215494A1

公开(公告)日：2023-07-06

申请号：US17565951

申请日：2021-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomohiko Yamagishi ,  Seiji Narui ,  Kiyoshi Nakai ,  Takamasa Suzuki

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C29/42

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C29/42

Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.

公开(公告)号：US20220199137A1

公开(公告)日：2022-06-23

申请号：US17563389

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C11/22 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G11C7/12 ,  G11C7/08

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US20220114049A1

公开(公告)日：2022-04-14

申请号：US17480714

申请日：2021-09-21

Applicant: Micron Technology, Inc.

Inventor： Kiyoshi Nakai

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.

公开(公告)号：US11132253B2

公开(公告)日：2021-09-28

申请号：US16211980

申请日：2018-12-06

Applicant: Micron Technology, Inc.

Inventor： Kiyoshi Nakai

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.

公开(公告)号：US11709731B2

公开(公告)日：2023-07-25

申请号：US17318741

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Kiyoshi Nakai

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/45 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/45

Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.

公开(公告)号：US20210012825A1

公开(公告)日：2021-01-14

申请号：US16508772

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C11/22 ,  G11C11/408 ,  G11C11/4091

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US20250087262A1

公开(公告)日：2025-03-13

申请号：US18752008

申请日：2024-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kiyoshi Nakai

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  H01L23/48 ,  H03K19/20

Abstract: Embodiments of the disclosure provide an apparatus comprising: a plurality of TSVs; a plurality of core dies stacked with one another; and an output control circuit. Each core die includes a data output circuit coupled to one or more TSVs to output read data. The data output circuit includes a data splitter to provide first and second complementary read data in parallel based on the read data, an output data latch to latch the first and second read data, and an output data buffer to receive the first and second read data from the output data latch and drive the TSVs based on the first and second read data. The output control circuit provides a first reset signal to the output data buffer and a second reset signal to the data splitter or the output data buffer to disable the output of the read data to the TSVs.

公开(公告)号：US11854601B2

公开(公告)日：2023-12-26

申请号：US17563878

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kiyoshi Nakai ,  Seiji Narui

IPC: G11C11/4076 ,  H01L25/065 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  H01L2225/06541

Abstract: Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die.

公开(公告)号：US20200183782A1

公开(公告)日：2020-06-11

申请号：US16212017

申请日：2018-12-06

Applicant: Micron Technology, Inc.

Inventor： Kiyoshi Nakai

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/45

Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.

公开(公告)号：US11869580B2

公开(公告)日：2024-01-09

申请号：US17565951

申请日：2021-12-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomohiko Yamagishi ,  Seiji Narui ,  Kiyoshi Nakai ,  Takamasa Suzuki

IPC: G11C11/4096 ,  G11C29/42 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4093 ,  G11C29/42

Abstract: Apparatuses, systems, and methods for counter based read clocks in stacked memory devices. An interface die provides a read command to a core die, which reads data with timing based on the read command provides that data to a read FIFO circuit of the core die. A delay time after providing the read command, the interface die begins providing a counter-based clock signal which operates an output of the read FIFO. The counter-based clock signal operates on a different time domain (e.g., a faster frequency) than the timing of the read command.