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    Parallel access in a memory array
    1.
    发明授权
    Parallel access in a memory array 有权

    公开(公告)号：US12300305B2

    公开(公告)日：2025-05-13

    申请号：US18582185

    申请日：2024-02-20

    Applicant: Micron Technology, Inc.

    Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

    IPC: G11C8/00 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

    Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

    Circuit partitioning for a memory device
    2.
    发明授权
    Circuit partitioning for a memory device 有权

    公开(公告)号：US12182432B2

    公开(公告)日：2024-12-31

    申请号：US17493988

    申请日：2021-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

    IPC: G11C11/22 ,  G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/52

    Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

    Techniques for parallel memory cell access
    5.
    发明授权
    Techniques for parallel memory cell access 有权

    公开(公告)号：US11948638B2

    公开(公告)日：2024-04-02

    申请号：US17651216

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Andrea Martinelli ,  Maurizio Rizzi

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

    CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3404

    Abstract: Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.

    TOGGLING KNOWN PATTERNS FOR READING MEMORY CELLS IN A MEMORY DEVICE
    7.
    发明公开
    TOGGLING KNOWN PATTERNS FOR READING MEMORY CELLS IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240012576A1

    公开(公告)日：2024-01-11

    申请号：US17861680

    申请日：2022-07-11

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Martinelli ,  Ferdinando Bedeschi

    IPC: G06F3/06 ,  G11C13/00

    CPC classification number: G06F3/0655 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/0652

    Abstract: Systems, methods, and apparatus for a memory device. In one approach, known reference patterns are stored in a memory array. The patterns are associated with codewords stored in the memory array. A first pattern has all memory cells written to a first logic state (e.g., all logic ones), and a second pattern has all memory cells written to an opposite second logic state (e.g., all logic zeros). When a controller reads a codeword, the controller first reads memory cells of the associated reference patterns to determine data for estimating a threshold voltage distribution of memory cells in the codeword. Based on a number of memory cells of the reference patterns that snap when reading the first and second patterns, the controller selects a read voltage for reading the associated codeword.

    ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE
    9.
    发明申请
    ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE 有权

    公开(公告)号：US20220129058A1

    公开(公告)日：2022-04-28

    申请号：US17573194

    申请日：2022-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Graziano Mirichigni

    IPC: G06F1/3225 ,  G06F1/3234 ,  G06F9/4401 ,  G06F1/3287

    Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

    Architecture-based power management for a memory device
    10.
    发明授权
    Architecture-based power management for a memory device 有权

    公开(公告)号：US11243596B2

    公开(公告)日：2022-02-08

    申请号：US16551597

    申请日：2019-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Graziano Mirichigni

    IPC: G06F1/32 ,  G06F9/44 ,  G06F1/3225 ,  G06F1/3234 ,  G06F9/4401 ,  G06F1/3287

    Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

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