公开(公告)号：US20240185406A1

公开(公告)日：2024-06-06

申请号：US18438256

申请日：2024-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yutao Gong ,  Dmitry Vengertsev ,  Seth A. Eichmeyer ,  Jing Gong

IPC: G06T7/00 ,  G01N21/88 ,  G01N21/95 ,  G06V10/762 ,  G06V10/764 ,  G06V10/776 ,  G06V10/82 ,  H01L21/67

CPC classification number: G06T7/0004 ,  G01N21/9501 ,  G06T7/001 ,  G06V10/762 ,  G06V10/764 ,  G06V10/776 ,  G06V10/82 ,  G01N2021/8887 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148 ,  H01L21/67288

Abstract: An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may be formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.

公开(公告)号：US11869620B2

公开(公告)日：2024-01-09

申请号：US17647508

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

IPC: G11C29/00 ,  G11C11/408

CPC classification number: G11C29/70 ,  G11C11/4082

Abstract: Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.

公开(公告)号：US11114181B1

公开(公告)日：2021-09-07

申请号：US16983757

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer ,  Kenji Yoshida

IPC: G11C29/00 ,  G11C29/44

Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of memory cells partitioned into a number of memory segments. Each of the number of memory segments may include a redundant memory-cell group configurable to be accessed instead of a defective memory-cell group of the memory segment. The memory device may also include a set of latches configurable to indicate that a redundant memory-cell group of a memory segment of the number of memory segments is to be accessed instead of a defective memory-cell group of the memory segment. The set of latches may include segment latches configurable to indicate the memory segment or a status of the set of latches. The set of latches may also include address latches configurable to indicate the defective memory-cell group within the memory segment. Related systems and methods are also disclosed.

公开(公告)号：US20250061017A1

公开(公告)日：2025-02-20

申请号：US18781064

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： John M. Gonzales ,  Christopher G. Wieduwilt ,  Seth A. Eichmeyer ,  Matthew D. Jenkinson

IPC: G06F11/10 ,  G06F11/07

Abstract: Apparatuses, systems, and methods for correcting latch upset events in a trim register are described. An example method includes sending a command, from a controller, to access at least one block of a plurality of blocks of a non-volatile memory. The method can further include receiving a failure message associated with reading the at least one block. The method can further include, in response to receiving the failure message, resetting trim data associated with the plurality of blocks.

公开(公告)号：US11922613B2

公开(公告)日：2024-03-05

申请号：US16925243

申请日：2020-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yutao Gong ,  Dmitry Vengertsev ,  Seth A. Eichmeyer ,  Jing Gong

IPC: G06T7/00 ,  G01N21/95 ,  G06V10/762 ,  G06V10/764 ,  G06V10/776 ,  G06V10/82 ,  G01N21/88 ,  H01L21/67

CPC classification number: G06T7/0004 ,  G01N21/9501 ,  G06T7/001 ,  G06V10/762 ,  G06V10/764 ,  G06V10/776 ,  G06V10/82 ,  G01N2021/8887 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148 ,  H01L21/67288

Abstract: An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may be formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.

公开(公告)号：US20220366224A1

公开(公告)日：2022-11-17

申请号：US17319765

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Dmitry Vengertsev ,  Seth A. Eichmeyer ,  Jing Gong ,  John Christopher M. Sancon ,  Nicola Ciocchini ,  Tom Tangelder

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

Abstract: Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the binary neural network and perform operations consistent with the binary neural network. The weights of the binary neural network can correspond to non-zero values.

公开(公告)号：US11069426B1

公开(公告)日：2021-07-20

申请号：US16796511

申请日：2020-02-20

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

IPC: G11C29/00 ,  G11C11/408 ,  G11C11/406

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes a plurality of banks that each include (1) a plurality of memory cells and (2) a plurality of redundant cells configured to replace one or more target memory cells in the plurality of memory cells. A set of shared fuses and latches may be used to store a row address for each repair that may be implemented in one of the plurality of banks. A shared match circuit coupled to the set of shared latches and the plurality of memory banks may be configured to at least partially implement a row repair for the row address for a bank associated with a commanded operation.

公开(公告)号：US20210201460A1

公开(公告)日：2021-07-01

申请号：US16925243

申请日：2020-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yutao Gong ,  Dmitry Vengertsev ,  Seth A. Eichmeyer ,  Jing Gong

IPC: G06T7/00 ,  G01N21/95

Abstract: An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may he formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.

公开(公告)号：US20250061058A1

公开(公告)日：2025-02-20

申请号：US18778600

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： John M. Gonzales ,  Christopher G. Wieduwilt ,  Seth A. Eichmeyer ,  Matthew D. Jenkinson

IPC: G06F12/02 ,  G06F11/10

Abstract: Apparatuses, systems, and methods for block status parity data are described. An example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. The example method further comprises storing parity data that corresponds to the block status data. The example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.

公开(公告)号：US20250061016A1

公开(公告)日：2025-02-20

申请号：US18784572

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： John M. Gonzales ,  Christopher G. Wieduwilt ,  Seth A. Eichmeyer ,  Matthew D. Jenkinson

IPC: G06F11/10

Abstract: Apparatuses, systems, and methods for block status data reset are described. An example method includes sending a command, from a controller, to access at least one block of a first memory device. The example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. The example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.