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公开(公告)号：US20240185406A1
公开(公告)日：2024-06-06
申请号：US18438256
申请日：2024-02-09
发明人： Yutao Gong , Dmitry Vengertsev , Seth A. Eichmeyer , Jing Gong
IPC分类号： G06T7/00 , G01N21/88 , G01N21/95 , G06V10/762 , G06V10/764 , G06V10/776 , G06V10/82 , H01L21/67
CPC分类号： G06T7/0004 , G01N21/9501 , G06T7/001 , G06V10/762 , G06V10/764 , G06V10/776 , G06V10/82 , G01N2021/8887 , G06T2207/20081 , G06T2207/20084 , G06T2207/30148 , H01L21/67288
摘要： An inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (CNN) to determine a classification from a plurality of classes for the captured image. Each of the plurality of classes indicates a type of a defect in the wafer. The system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. The system may also include a classification system to determine a classification from the plurality of classes for the training image. The encoder and decoder may be formed from a CNN autoencoder. The classification CNN and the CNN autoencoder may each be a deep neural network.
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公开(公告)号：US11869620B2
公开(公告)日：2024-01-09
申请号：US17647508
申请日：2022-01-10
IPC分类号： G11C29/00 , G11C11/408
CPC分类号： G11C29/70 , G11C11/4082
摘要： Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.
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公开(公告)号：US11114181B1
公开(公告)日：2021-09-07
申请号：US16983757
申请日：2020-08-03
摘要： Memory devices are disclosed. A memory device may include a memory array including a number of memory cells partitioned into a number of memory segments. Each of the number of memory segments may include a redundant memory-cell group configurable to be accessed instead of a defective memory-cell group of the memory segment. The memory device may also include a set of latches configurable to indicate that a redundant memory-cell group of a memory segment of the number of memory segments is to be accessed instead of a defective memory-cell group of the memory segment. The set of latches may include segment latches configurable to indicate the memory segment or a status of the set of latches. The set of latches may also include address latches configurable to indicate the defective memory-cell group within the memory segment. Related systems and methods are also disclosed.
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公开(公告)号：US20240201252A1
公开(公告)日：2024-06-20
申请号：US18535640
申请日：2023-12-11
IPC分类号： G01R31/311
CPC分类号： G01R31/311
摘要： An example method can include focusing a light source onto a circuit of a first memory die of a plurality of memory dies. A light of the light source can reach the circuit of the memory die and can be reflected back toward a sensor. The method can further include receiving the reflection of light from the circuit at the sensor. The method can further include determining whether the circuit is transferring a particular signal based on the reflected light.
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公开(公告)号：US11829243B2
公开(公告)日：2023-11-28
申请号：US17572129
申请日：2022-01-10
CPC分类号： G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0793 , G06F11/3037
摘要： Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
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公开(公告)号：US11694762B2
公开(公告)日：2023-07-04
申请号：US17466160
申请日：2021-09-03
IPC分类号： G11C7/00 , G11C29/44 , G11C29/02 , G11C29/00 , H03M13/11 , G11C11/409 , H03M13/13 , G11C29/18
CPC分类号： G11C29/44 , G11C11/409 , G11C29/027 , G11C29/18 , G11C29/789 , H03M13/1105 , H03M13/13
摘要： Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.
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公开(公告)号：US20220139492A1
公开(公告)日：2022-05-05
申请号：US17647508
申请日：2022-01-10
IPC分类号： G11C29/00 , G11C11/408
摘要： Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.
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公开(公告)号：US20210110881A1
公开(公告)日：2021-04-15
申请号：US16599796
申请日：2019-10-11
摘要： Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.
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公开(公告)号：US20230315918A1
公开(公告)日：2023-10-05
申请号：US17706410
申请日：2022-03-28
摘要： A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
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公开(公告)号：US11244741B1
公开(公告)日：2022-02-08
申请号：US17089002
申请日：2020-11-04
IPC分类号： G11C29/00 , G11C11/40 , G11C11/408
摘要： Memory devices are disclosed. A memory device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, and electronic systems are also disclosed.
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