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    Concurrent compensation in a memory system
    1.
    发明授权
    Concurrent compensation in a memory system 有权

    公开(公告)号：US11967356B2

    公开(公告)日：2024-04-23

    申请号：US17350305

    申请日：2021-06-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

    IPC: G11C11/4076 ,  G11C11/408

    CPC classification number: G11C11/4076 ,  G11C11/4087

    Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

    Semiconductor device including fuse circuit
    3.
    发明授权
    Semiconductor device including fuse circuit 有权
    半导体装置包括熔丝电路

    公开(公告)号：US09431128B2

    公开(公告)日：2016-08-30

    申请号：US14635894

    申请日：2015-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Yusuke Sakamoto ,  Kenji Yoshida

    IPC: G11C17/16 ,  H03K19/177 ,  G11C17/18 ,  G11C29/00

    CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/789 ,  H03K19/17768

    Abstract: Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element, and a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage.

    Abstract translation: 本文公开了一种包括熔丝电路的装置，熔丝电路包括熔丝元件，熔丝电路被配置为提供响应于熔丝元件的状态的具有第一电压或第二电压的第一输出信号;以及感测电路， 第二输出信号具有响应于第一输出信号的第一电压或第三电压，第三电压不同于第二电压。

    CONCURRENT COMPENSATION IN A MEMORY SYSTEM
    7.
    发明申请
    CONCURRENT COMPENSATION IN A MEMORY SYSTEM 有权

    公开(公告)号：US20220406358A1

    公开(公告)日：2022-12-22

    申请号：US17350305

    申请日：2021-06-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

    IPC: G11C11/4076 ,  G11C11/408

    Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

    Memory devices with redundant memory cells for replacing defective memory cells, and related systems and methods
    8.
    发明授权
    Memory devices with redundant memory cells for replacing defective memory cells, and related systems and methods 有权

    公开(公告)号：US11114181B1

    公开(公告)日：2021-09-07

    申请号：US16983757

    申请日：2020-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer ,  Kenji Yoshida

    IPC: G11C29/00 ,  G11C29/44

    Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of memory cells partitioned into a number of memory segments. Each of the number of memory segments may include a redundant memory-cell group configurable to be accessed instead of a defective memory-cell group of the memory segment. The memory device may also include a set of latches configurable to indicate that a redundant memory-cell group of a memory segment of the number of memory segments is to be accessed instead of a defective memory-cell group of the memory segment. The set of latches may include segment latches configurable to indicate the memory segment or a status of the set of latches. The set of latches may also include address latches configurable to indicate the defective memory-cell group within the memory segment. Related systems and methods are also disclosed.

    Apparatus and methods for refreshing memory cells of a semiconductor device
    9.
    发明授权
    Apparatus and methods for refreshing memory cells of a semiconductor device 有权

    公开(公告)号：US10210922B2

    公开(公告)日：2019-02-19

    申请号：US15962886

    申请日：2018-04-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kenji Yoshida ,  Hiroki Fujisawa

    IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

    Abstract: Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

    Apparatuses and methods for refreshing memory cells of a semiconductor device
    10.
    发明授权
    Apparatuses and methods for refreshing memory cells of a semiconductor device 有权

    公开(公告)号：US09984738B2

    公开(公告)日：2018-05-29

    申请号：US15499568

    申请日：2017-04-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kenji Yoshida ,  Hiroki Fujisawa

    IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094

    CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

    Abstract: Apparatuses and methods for refreshing memory cells of semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

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