公开(公告)号：US20250095713A1

公开(公告)日：2025-03-20

申请号：US18958966

申请日：2024-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US09530459B2

公开(公告)日：2016-12-27

申请号：US14523704

申请日：2014-10-24

Applicant: Micron Technology, Inc.

Inventor： Shingo Mitsubori ,  Hiroki Fujisawa

IPC: G11C7/00 ,  G11C5/02 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C5/025 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Abstract translation: 本公开中公开的半导体存储器包括第一和第二存储器单元阵列，传送从第一存储单元阵列读取的读取数据的第一主数据线，传送从第二存储单元阵列读取的读取数据的第二主数据线 耦合到第二主数据线的主放大器，以及耦合到第一主数据线和第二主数据线的中继器电路。

公开(公告)号：US20240347102A1

公开(公告)日：2024-10-17

申请号：US18542581

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Ki-Jun Nam ,  Won Joo Yun ,  Shingo Mitsubori

IPC: G11C11/4093

CPC classification number: G11C11/4093

Abstract: Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.

公开(公告)号：US11557331B2

公开(公告)日：2023-01-17

申请号：US17030018

申请日：2020-09-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shingo Mitsubori ,  Hidekazu Noguchi

IPC: G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.

公开(公告)号：US10902904B1

公开(公告)日：2021-01-26

申请号：US16568082

申请日：2019-09-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shingo Mitsubori ,  Kenji Mae

IPC: G11C11/4093 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  H03K19/20

Abstract: Apparatuses and methods for providing multiphase clocks are disclosed. An example apparatus includes a plurality of clock circuits, each configured to provide one of the multiphase clocks responsive to a respective input clock. The apparatus further includes first and second control circuits. The first control circuit receives a first one of the multiphase clocks and a reset signal provided to the plurality of clock circuits, and provides a first control signal to reset a clock circuit of the plurality of clock circuits that is based on the first one of the multiphase clocks and the reset signal. The second control circuit receives the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks.

公开(公告)号：US20250157526A1

公开(公告)日：2025-05-15

申请号：US18780106

申请日：2024-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuichiro Sato ,  Shingo Mitsubori ,  Ryo Fujimaki

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

Abstract: An example apparatus includes a first circuit configured to receive a plurality of first write data and then a plurality of second write data responsive to a write command; a second circuit configured to select one or ones of the plurality of first write data and one or ones of the plurality of second write data based, at least in part, on a first selection signal and a second selection signal following the first selection signal, respectively; and a third circuit configured to: receive an internal write command signal provided correspondingly to the write command; mask a portion of the internal write command signal a timing of which partially overlaps the plurality of first write data to provide a masked internal write command signal; and provide the second selection signal based, at least in part, on the second internal command signal.

公开(公告)号：US12183385B2

公开(公告)日：2024-12-31

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4096 ,  G11C11/4076

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20240062803A1

公开(公告)日：2024-02-22

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.