公开(公告)号：US20220293598A1

公开(公告)日：2022-09-15

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220102351A1

公开(公告)日：2022-03-31

申请号：US17643316

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US20220013527A1

公开(公告)日：2022-01-13

申请号：US16924995

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01L21/3065

Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

公开(公告)号：US20200243537A1

公开(公告)日：2020-07-30

申请号：US16259634

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Yan Li ,  Song Guo ,  Mohd Kamran Akhtar ,  Alex J. Schrinsky

IPC: H01L27/108 ,  H01G4/08 ,  H01G4/012 ,  H01G4/008

Abstract: Methods, apparatuses, and systems related to forming a trench using a polymerizing radical material. An example method includes depositing a polymerizing radical material in a number of trenches formed over a substrate. The method further includes etching a portion of the deposited polymerizing radical material from the number of trenches. The example method further includes selectively etching into one of the number of trenches below the deposited polymerizing radical material. The one of the number of trenches is narrower than another of the number of trenches.

公开(公告)号：US11594536B2

公开(公告)日：2023-02-28

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210202487A1

公开(公告)日：2021-07-01

申请号：US16729076

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Shen Hu ,  Yan Li ,  Nicholas R. Tapias

IPC: H01L27/108 ,  G11C11/408

Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

公开(公告)号：US20200066730A1

公开(公告)日：2020-02-27

申请号：US16111499

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

IPC: H01L27/108 ,  H01L21/308

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

公开(公告)号：US20240074158A1

公开(公告)日：2024-02-29

申请号：US18234145

申请日：2023-08-15

Applicant: Micron Technology, Inc.

Inventor： Chunhua Yao ,  Song Guo ,  Vivek Yadav

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02

Abstract: A variety of applications can include an apparatus having a memory device in which, during fabrication of the memory device, processing a dielectric isolation region about an active area of a memory cell is controlled to provide enhanced electric isolation of a data line contact to the memory cell with respect to a cell contact to the memory cell. A portion of the dielectric isolation region can be recessed, creating a corner between the dielectric isolation region and a conductive region, where the conductive region is material for the active area. The corner can be filled with a dielectric material and the data line contact can be formed contacting the dielectric material and coupled to the conductive region. The cell contact can be formed to the memory cell contacting the dielectric material such that the dielectric material is between the cell contact and the data line contact.

公开(公告)号：US20230028297A1

公开(公告)日：2023-01-26

申请号：US17813076

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Silvia Borsari ,  Song Guo

IPC: H01L27/108

Abstract: A method of forming a semiconductor device comprising forming a silicon carbide material on a patterned material. The silicon carbide material is subjected to a plasma to expose horizontal portions of the silicon carbide material to the plasma. The horizontal portions of the silicon carbide material are selectively removed, and the patterned material is removed to form a pattern of the silicon carbide material.

公开(公告)号：US20230022071A1

公开(公告)日：2023-01-26

申请号：US17813080

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Chunhua Yao ,  Song Guo ,  Vivek Yadav

IPC: H01L27/108

Abstract: An apparatus comprising active areas and shallow trench isolation structures on a base material. A first conductive material is vertically adjacent to an active area of the active areas and between laterally adjacent shallow trench isolation structures. A second conductive material is vertically adjacent to the first conductive material and between the laterally adjacent shallow trench isolation structures. A silicon carbide material is on sidewalls of the shallow trench isolation structures and exhibits substantially vertical sidewalls. An oxide material is adjacent to the active areas and shallow trench isolation structures, a nitride material is adjacent to the oxide material, and a digit line is adjacent to the second conductive material. An electronic system and methods of forming an apparatus are also disclosed.