公开(公告)号：US20240355595A1

公开(公告)日：2024-10-24

申请号：US18634430

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Rachmat Wibowo ,  Mohd Kamran Akhtar ,  Grady S. Waldo

IPC: H01J37/32

CPC classification number: H01J37/32724 ,  H01J37/32816 ,  H01J2237/327 ,  H01J2237/3341

Abstract: Methods, systems, and devices for low parameter plasma ashing techniques are described. The method may include performing an etching process on a substrate comprising a photoresist layer. In some cases, the method may include selecting at least a temperature of a clamp for holding the substrate, a temperature of a process chamber configured to perform the plasma ashing process, a pressure of the process chamber, and a power of a plasma source based at least in part on performing the etching process. The method may further include generating a plasma that comprises oxygen, applying the plasma to the photoresist layer, and exposing the photoresist layer of the substrate to the plasma at the selected temperature, pressure, and power to at least partially remove the photoresist layer from the substrate.

公开(公告)号：US20240315018A1

公开(公告)日：2024-09-19

申请号：US18676056

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11239240B2

公开(公告)日：2022-02-01

申请号：US16902783

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

IPC: G11C11/24 ,  H01L27/108 ,  H01L21/764 ,  G11C11/408 ,  G11C11/4091

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

公开(公告)号：US10707215B2

公开(公告)日：2020-07-07

申请号：US16109215

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

IPC: G11C11/24 ,  H01L27/108 ,  H01L21/764 ,  G11C11/408 ,  G11C11/4091

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.

公开(公告)号：US10665665B2

公开(公告)日：2020-05-26

申请号：US16167016

申请日：2018-10-22

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/108 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/67

Abstract: Systems, apparatuses, and methods related to passivation material for a pillar adjacent a trench are described. An example method includes forming a passivation material on a top region of a pillar adjacent a trench of a semiconductor device and removing a first portion of the passivation material to form, on a remaining second portion of the passivation material, a surface that is coplanar with an underlying sidewall of the pillar. The example method further includes removing a portion of a substrate material at a bottom region of the trench and removing the remaining second portion of the passivation material from the top region.

公开(公告)号：US20190378843A1

公开(公告)日：2019-12-12

申请号：US16419978

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Mohd Kamran Akhtar ,  Silvia Borsari ,  Alex J. Schrinsky

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

公开(公告)号：US20250142820A1

公开(公告)日：2025-05-01

申请号：US19009060

申请日：2025-01-03

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230077163A1

公开(公告)日：2023-03-09

申请号：US18050431

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Troy R. Sorensen ,  Mohd Kamran Akhtar

IPC: H01L27/11548 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11575

Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.

公开(公告)号：US20220285357A1

公开(公告)日：2022-09-08

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20200312857A1

公开(公告)日：2020-10-01

申请号：US16902783

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Arzum F. Simsek-Ege ,  Guangjun Yang ,  Kuo-Chen Wang ,  Mohd Kamran Akhtar ,  Katsumi Koge

IPC: H01L27/108 ,  H01L21/764 ,  G11C11/408

Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.