公开(公告)号：US11594536B2

公开(公告)日：2023-02-28

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230141716A1

公开(公告)日：2023-05-11

申请号：US17453727

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Hyuck Soo Yang ,  Byung Yoon Kim ,  Yong Mo Yang ,  Shivani Srivastava

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/42364 ,  H01L21/28194 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/10897

Abstract: Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

公开(公告)号：US20220293598A1

公开(公告)日：2022-09-15

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210327881A1

公开(公告)日：2021-10-21

申请号：US16851588

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Ke-Hung Chen ,  Christopher W. Petz ,  Pankaj Sharma ,  Yong Mo Yang

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/07

Abstract: Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12199094B2

公开(公告)日：2025-01-14

申请号：US17453727

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Hyuck Soo Yang ,  Byung Yoon Kim ,  Yong Mo Yang ,  Shivani Srivastava

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H10B12/00

Abstract: Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.