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公开(公告)号：US20240290389A1
公开(公告)日：2024-08-29
申请号：US18654697
申请日：2024-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
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公开(公告)号：US11967387B2
公开(公告)日：2024-04-23
申请号：US17970459
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Vinh Q. Diep , Zhengyi Zhang , Yingda Dong
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/10 , G11C16/30
Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
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公开(公告)号：US20220199175A1
公开(公告)日：2022-06-23
申请号：US17249433
申请日：2021-03-02
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Vinh Q. Diep , Zhengyi Zhang , Yingda Dong
Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
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公开(公告)号：US20210366558A1
公开(公告)日：2021-11-25
申请号：US17443370
申请日：2021-07-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhengyi Zhang , Dan Xu , Tomoko Ogura Iwasaki
Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.
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公开(公告)号：US12254927B2
公开(公告)日：2025-03-18
申请号：US18654697
申请日：2024-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
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Patent Agency Ranking
公开(公告)号：US20230044240A1
公开(公告)日：2023-02-09
申请号：US17970459
申请日：2022-10-20
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Vinh Q. Diep , Zhengyi Zhang , Yingda Dong
Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
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公开(公告)号：US11538535B2
公开(公告)日：2022-12-27
申请号：US17443370
申请日：2021-07-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhengyi Zhang , Dan Xu , Tomoko Ogura Iwasaki
Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.
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公开(公告)号：US20210202013A1
公开(公告)日：2021-07-01
申请号：US16895025
申请日：2020-06-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhengyi Zhang , Dan Xu , Tomoko Ogura Iwasaki
Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.
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公开(公告)号：US12014778B2
公开(公告)日：2024-06-18
申请号：US17670037
申请日：2022-02-11
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang , Tomoko Ogura Iwasaki
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3459
Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.
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公开(公告)号：US20230207018A1
公开(公告)日：2023-06-29
申请号：US18077681
申请日：2022-12-08
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Zhengyi Zhang
CPC classification number: G11C16/102 , G11C16/16 , G11C16/0433 , G11C16/3459
Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a selected wordline associated with a set of memory cells to be programmed to a target voltage level representing a programming level. Voltage levels of the selected wordline and one or more unselected wordlines of the memory array are discharged to approximately a ground voltage level and a bitline voltage level is applied to a bitline corresponding to the programming level. The selected wordline and a set of unselected wordlines are charged to approximately a pass voltage level followed by the discharge of the selected wordline to a reverse bias level to establish an erase voltage level on the set of memory cells. The control logic further performs a program verify operation corresponding to the programming level associated with the set of memory cells.
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