公开(公告)号：US09171636B2

公开(公告)日：2015-10-27

申请号：US13940010

申请日：2013-07-11

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin Chang ,  Wen-Wei Yeh ,  Chih-Shen Chang ,  Hang-Ting Lue

IPC: G11C16/00 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/3427

Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。

公开(公告)号：US09490017B2

公开(公告)日：2016-11-08

申请号：US14643907

申请日：2015-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Wen-Wei Yeh

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3472

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset. Word line-side inhibit voltages are applied to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 存储单元块包括多个具有第一串选择开关和第二串选择开关之间的通道线的NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选块中所选择的字线集合的选定子集，以诱导耦合到所选子集的存储器单元中的隧穿。 字线侧抑制电压被施加到所选块中的字线组的未选择子集，以抑制耦合到未选择子集的存储器单元中的隧穿。

公开(公告)号：US09177662B1

公开(公告)日：2015-11-03

申请号：US14481953

申请日：2014-09-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wen-Wei Yeh ,  Chih-Shen Chang ,  Kuo-Pin Chang

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10

Abstract: A pre-reading method and a programming method for a 3D NAND flash memory are provided. The pre-reading method comprises the following steps. A selected string includes a first memory cell, two second memory cells and a plurality of third memory cells. The two second memory cells are adjacent to the first memory cell. The third memory cells are not adjacent to the first memory cell. A first pass voltage is applied on the second memory cells, a second pass voltage is applied on the third memory cells, and a read voltage is applied on the first memory cell via a plurality of word lines for reading a data of the first memory cell. The first pass voltage is larger than the second pass voltage.

Abstract translation: 提供了一种用于3D NAND闪存的预读方法和编程方法。 预读方法包括以下步骤。 所选择的串包括第一存储器单元，两个第二存储器单元和多个第三存储器单元。 两个第二存储单元与第一存储单元相邻。 第三存储单元不与第一存储单元相邻。 对第二存储单元施加第一通过电压，在第三存储单元施加第二通过电压，并且经由用于读取第一存储单元的数据的多条字线将读取电压施加在第一存储单元上 。 第一通过电压大于第二通过电压。

公开(公告)号：US20140211563A1

公开(公告)日：2014-07-31

申请号：US13940010

申请日：2013-07-11

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin Chang ,  Wen-Wei Yeh ,  Chih-Shen Chang ,  Hang-Ting Lue

IPC: G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/3427

Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。