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公开(公告)号：US20110291224A1
公开(公告)日：2011-12-01
申请号：US13198581
申请日：2011-08-04
IPC分类号： H01L29/02
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。
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公开(公告)号：US08450829B2
公开(公告)日：2013-05-28
申请号：US13198581
申请日：2011-08-04
IPC分类号： H01L21/70
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。
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公开(公告)号：US20100112489A1
公开(公告)日：2010-05-06
申请号：US12687005
申请日：2010-01-13
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。
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公开(公告)号：US20080070165A1
公开(公告)日：2008-03-20
申请号：US11521851
申请日：2006-09-14
IPC分类号： G03F7/26
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。
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公开(公告)号：US08012674B2
公开(公告)日：2011-09-06
申请号：US12687005
申请日：2010-01-13
IPC分类号： G03F7/26
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。
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公开(公告)号：US07666578B2
公开(公告)日：2010-02-23
申请号：US11521851
申请日：2006-09-14
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。
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公开(公告)号：US10824636B2
公开(公告)日：2020-11-03
申请号：US14722330
申请日：2015-05-27
申请人： Mark Fischer , Prakash Khot , Dilip Kumar Vedula , Tong Zhao , Siva Prakash Ragavan , Joseph Paquette
发明人： Mark Fischer , Prakash Khot , Dilip Kumar Vedula , Tong Zhao , Siva Prakash Ragavan , Joseph Paquette
IPC分类号： G06F16/25 , G06F16/2455 , G06F16/2458 , G06F16/2452 , G06F16/27
摘要： Computer implemented techniques for storage management include receiving a query from an application within an application level, which is received as a standard syntax wrapped query language query, with the standard syntax wrapped query having as a parameter, an identifier to a specific object, determining a platform type on which the received query is executable and translating the standard syntax wrapped query language query into the determined native query language used by the determined data storage platform type.
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8.发明授权公开(公告)号：US08954173B1
公开(公告)日：2015-02-10
申请号：US12203739
申请日：2008-09-03
申请人： Mark Fischer
发明人： Mark Fischer
CPC分类号： G06F17/148 , A01K29/005 , A61B5/726 , G06K9/00516 , G06K9/00536 , G10L17/26 , H04N19/63
摘要： A method and apparatus for profiling and identifying the source of a signal is provided. A first method includes receiving a signal produced by a known source and creating a matrix of wavelet coefficients corresponding to a wavelet transform of the signal. The method also includes profiling the signal according to an output of a wavelet transform utilizing a particular base function and a particular scale set. A second method includes performing a wavelet transform having a particular profile on a received signal and determining the presence of a particular signal-producing entity as a function of wavelet coefficients exceeding a threshold. An apparatus includes a receiver configured to receive a signal and a processor coupled to the receiver, such that the processor is configured to perform wavelet transforms on the signals. A database is coupled to the processor and configured to store wavelet transform profiles.
摘要翻译： 提供了一种用于分析和识别信号源的方法和装置。 第一种方法包括接收由已知源产生的信号并产生对应于信号的小波变换的小波系数矩阵。 该方法还包括根据使用特定基本函数和特定比例集的小波变换的输出对信号进行分析。 第二种方法包括在接收到的信号上执行具有特定分布的小波变换，并且确定特定信号产生实体的存在作为超过阈值的小波系数的函数。 一种装置包括被配置为接收信号的接收机和耦合到接收机的处理器，使得处理器被配置为对信号执行小波变换。 数据库耦合到处理器并被配置为存储小波变换简档。
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公开(公告)号：US08883575B2
公开(公告)日：2014-11-11
申请号：US13440383
申请日：2012-04-05
IPC分类号： H01L21/336 , H01L21/467 , H01L21/84 , H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7853 , Y10S438/947
摘要： A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.
摘要翻译： 工艺可以包括在衬底上直接在选择为初始半导体鳍片的区域之上和之上形成掩模，并且减少形成从初始半导体鳍片横向变薄的半导体鳍片的初始半导体鳍片。 可以进行该处理，使得掩模在横向上比垂直方向更大程度地退回。 在各种实施例中，该方法可以包括从散热片半导体去除材料以实现已经在横向退绕的掩模的阴影之下的减薄的半导体鳍片。 电子器件可以包括作为半导体器件的一部分的变薄的半导体鳍片。
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公开(公告)号：US20120241832A1
公开(公告)日：2012-09-27
申请号：US13490369
申请日：2012-06-06
申请人： Mark Fischer
发明人： Mark Fischer
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/0207 , H01L27/10873
摘要： The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.
摘要翻译： 本发明包括与鳍式场效应晶体管（finFET）技术结合使用部分绝缘体上硅（SOI）技术的方法，以形成特别适用于动态随机存取存储器（DRAM）阵列的晶体管。 本发明还包括具有低刷新率的DRAM阵列。 另外，本发明包括含有水平相对的源极/漏极区域和在源极/漏极区域之间的沟道区域的晶体管的半导体构造。 晶体管可以包括围绕通道区域的至少部分的至少四分之三的栅极，并且在一些方面可包括围绕通道区域的至少部分的整体的栅极。
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