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41 条记录 (耗时 0.054 秒)

    HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE
    1.
    发明申请
    HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE 有权
    使用热退火衬底的高电阻SOI衬底波形

    公开(公告)号：US20090110898A1

    公开(公告)日：2009-04-30

    申请号：US11931371

    申请日：2007-10-31

    申请人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    发明人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    IPC分类号： H01L21/30 ,  B32B7/02 ,  B32B9/00 ,  B32B9/04

    CPC分类号： H01L21/76254 ,  H01L21/76256 ,  H01L29/78603 ,  Y10T428/249921 ,  Y10T428/31504

    摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.

    摘要翻译： 提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。 具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率 （HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。

    High resistivity SOI base wafer using thermally annealed substrate
    2.
    发明授权
    High resistivity SOI base wafer using thermally annealed substrate 有权
    使用热退火基板的高电阻率SOI基底晶片

    公开(公告)号：US07883990B2

    公开(公告)日：2011-02-08

    申请号：US11931371

    申请日：2007-10-31

    申请人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    发明人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    IPC分类号： H01L21/762 ,  H01L21/46

    CPC分类号： H01L21/76254 ,  H01L21/76256 ,  H01L29/78603 ,  Y10T428/249921 ,  Y10T428/31504

    摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.

    摘要翻译： 提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。 具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率 （HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。

    SOLAR CELL CLASSIFICATION METHOD
    5.
    发明申请
    SOLAR CELL CLASSIFICATION METHOD 审中-公开
    太阳能电池分类方法

    公开(公告)号：US20120160295A1

    公开(公告)日：2012-06-28

    申请号：US13167792

    申请日：2011-06-24

    申请人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Kevin S. Petrarca ,  Gerd Pfeiffer ,  Kevin Prettyman ,  Brian C. Sapp

    发明人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Kevin S. Petrarca ,  Gerd Pfeiffer ,  Kevin Prettyman ,  Brian C. Sapp

    IPC分类号： H01L31/042 ,  H01L31/18 ,  G01R31/10

    CPC分类号： H02S50/10

    摘要： A method for characterizing the electronic properties of a solar cell to be used in a photovoltaic module comprises the steps of performing a room temperature IV curve measurement of the solar cell and classifying the solar cell based on this IV curve measurement. In order to take stress-related effects into account, the solar cells are reclassified depending on the result of an additional measurement conducted on the solar cells under stress. This stress-related measurement may be gained from light induced thermography (LIT) yielding information on diode shunt areas within the solar cell.

    摘要翻译： 用于表征在光伏模块中使用的太阳能电池的电子特性的方法包括以下步骤：基于该IV曲线测量，执行太阳能电池的室温IV曲线测量并对太阳能电池进行分类。 为了考虑应力相关的影响，太阳能电池根据在应力下对太阳能电池进行的额外测量的结果重新分类。 该应力相关测量可以从光诱导热成像（LIT）获得，产生关于太阳能电池内的二极管分流区域的信息。

    Silicon solar cell manufacture
    9.
    发明授权
    Silicon solar cell manufacture 有权
    硅太阳能电池制造

    公开(公告)号：US08735212B2

    公开(公告)日：2014-05-27

    申请号：US12866737

    申请日：2009-01-13

    申请人： Rainer Klaus Krause ,  Gerd Pfeiffer ,  Hans-Juergen Eickelmann ,  Thorsten Muehge

    发明人： Rainer Klaus Krause ,  Gerd Pfeiffer ,  Hans-Juergen Eickelmann ,  Thorsten Muehge

    IPC分类号： H01L31/0224

    CPC分类号： H01L31/022433 ,  H01L31/0475 ,  H01L31/0508 ,  Y02E10/50

    摘要： A silicon solar cell is manufactured by providing a carrier plate, and by applying a first contact pattern to the carrier plate. The first contact pattern includes a set of first laminar contacts. The silicon solar cell is further manufactured by applying a multitude of silicon slices to the first contact pattern, and by applying a second contact pattern to the multitude of silicon slices. Each first laminar contact of the set of first laminar contacts is in spatial laminar contact with maximally two silicon slices. The second contact pattern includes a set of second laminar contacts. Each second laminar contact of the set of second laminar contacts is in spatial laminar contact with maximally two silicon slices.

    摘要翻译： 硅太阳能电池通过提供载体板并且通过向载体板施加第一接触图案来制造。 第一接触图案包括一组第一层状接触。 硅太阳能电池进一步通过将多个硅片施加到第一接触图案并且通过向多个硅片施加第二接触图案而制造。 该组第一层状接触件的每个第一层状接触件与最多两个硅片片层叠接触。 第二接触图案包括一组第二层状接触。 该组第二层状接触件的每个第二层状接触件与最多两个硅片片层叠接触。