公开(公告)号：US12132126B2

公开(公告)日：2024-10-29

申请号：US17836822

申请日：2022-06-09

Applicant: Maxeon Solar Pte. Ltd.

Inventor： Richard Hamilton Sewell ,  Robert Woehl ,  Jens Dirk Moschner ,  Nils-Peter Harder

IPC: H01L31/044 ,  H01L31/0224 ,  H01L31/068

CPC classification number: H01L31/022441 ,  H01L31/0682 ,  Y02E10/547

Abstract: Approaches for fabricating wire-based metallization for solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a back surface and an opposing light-receiving surface. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the back surface of the substrate. A conductive contact structure is disposed on the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal wires. Each metal wire of the plurality of metal wires is parallel along a first direction to form a one-dimensional layout of a metallization layer for the solar cell.

公开(公告)号：US12074232B2

公开(公告)日：2024-08-27

申请号：US15362045

申请日：2016-11-28

Applicant: Maxeon Solar Pte. Ltd.

Inventor： Staffan Westerberg ,  Seung Bum Rim

IPC: H01L31/00 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0236 ,  H01L31/028 ,  H01L31/0288 ,  H01L31/0368 ,  H01L31/0376 ,  H01L31/068 ,  H01L31/18 ,  H01L31/20

CPC classification number: H01L31/02167 ,  H01L31/02168 ,  H01L31/022441 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/0288 ,  H01L31/03682 ,  H01L31/03762 ,  H01L31/0682 ,  H01L31/182 ,  H01L31/1868 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/50

Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating a multi-purpose passivation and contact layer, and resulting solar cells, are described. In an example, a solar cell includes a substrate having a light-receiving surface and a back surface. A P-type emitter region is disposed on the back surface of the substrate. An N-type emitter region is disposed in a trench formed in the back surface of the substrate. An N-type passivation layer is disposed on the N-type emitter region. A first conductive contact structure is electrically connected to the P-type emitter region. A second conductive contact structure is electrically connected to the N-type emitter region and is in direct contact with the N-type passivation layer.

公开(公告)号：US11996494B2

公开(公告)日：2024-05-28

申请号：US18099271

申请日：2023-01-20

Applicant: JIANGSU RUNERGY CENTURY PHOTOVOLTAIC TECHNOLOGY CO., LTD.

Inventor： Yang Yang ,  Rulong Chen ,  Yanbin Zhu ,  Haibo Li ,  Zhuojian Yang ,  Longzhong Tao

IPC: H01L31/18 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0236 ,  H01L31/0368 ,  H01L31/068

CPC classification number: H01L31/182 ,  H01L31/02168 ,  H01L31/022441 ,  H01L31/02363 ,  H01L31/03682 ,  H01L31/0682 ,  H01L31/1868 ,  H01L31/1872

Abstract: A preparation method of a low-cost passivated contact full-back electrode solar cell includes: performing alkali polishing on a Si wafer; performing RCA cleaning and HF cleaning; growing a tunnel SiOx film layer, an in-situ doped amorphous Si film layer, and a texturing mask layer on the back of the Si wafer; performing annealing activation on the amorphous Si film layer to form a polycrystalline Si film layer; etching the texturing mask layer; performing double-sided texturing on the Si wafer; performing HF cleaning to remove the texturing mask layer; depositing an AlOx film on the front and back of the Si wafer; depositing a SiNx passivation film on the front and back of the Si wafer; ablating a part of the AlOx film and a part of the SiNx passivation film on the back of the Si wafer; and performing screen-printing and sintering on the back of the Si wafer.

公开(公告)号：US11967657B2

公开(公告)日：2024-04-23

申请号：US16841541

申请日：2020-04-06

Applicant: Maxeon Solar Pte. Ltd.

Inventor： Gabriel Harley ,  Taeseok Kim ,  Richard Hamilton Sewell ,  Michael Morse ,  David D. Smith ,  Matthieu Moors ,  Jens-Dirk Moschner

IPC: H01L31/0224 ,  H01L31/0236 ,  H01L31/028 ,  H01L31/0475 ,  H01L31/05 ,  H01L31/068 ,  H01L31/0745

CPC classification number: H01L31/02245 ,  H01L31/022441 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/0475 ,  H01L31/0512 ,  H01L31/0516 ,  H01L31/0682 ,  H01L31/0745 ,  Y02E10/50 ,  Y02E10/547 ,  Y02P70/50

Abstract: Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions.

公开(公告)号：US11935972B2

公开(公告)日：2024-03-19

申请号：US17738984

申请日：2022-05-06

Applicant: Maxeon Solar Pte. Ltd.

Inventor： Kieran Mark Tracy ,  David D. Smith ,  Venkatasubramani Balu ,  Asnat Masad ,  Ann Waldhauer

IPC: H01L31/0224 ,  H01L31/0236 ,  H01L31/0352 ,  H01L31/05 ,  H01L31/068 ,  H01L31/0745 ,  H01L31/0747 ,  H01L31/18 ,  H01L31/20

CPC classification number: H01L31/022441 ,  H01L31/022425 ,  H01L31/022458 ,  H01L31/02363 ,  H01L31/035281 ,  H01L31/0516 ,  H01L31/0682 ,  H01L31/0745 ,  H01L31/0747 ,  H01L31/18 ,  H01L31/1804 ,  H01L31/202 ,  Y02E10/50 ,  Y02E10/546 ,  Y02E10/547 ,  Y02E10/548

Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

公开(公告)号：US20240072196A1

公开(公告)日：2024-02-29

申请号：US18504972

申请日：2023-11-08

Applicant: JINKO SOLAR (HAINING) CO., LTD. ,  ZHEJIANG JINKO SOLAR CO., LTD.

Inventor： Menglei XU ,  Jie YANG ,  Xinyu ZHANG ,  Hao JIN

IPC: H01L33/00 ,  H01L31/0216 ,  H01L31/0236 ,  H01L31/068 ,  H01L31/18 ,  H01L33/44

CPC classification number: H01L33/0016 ,  H01L31/02167 ,  H01L31/02168 ,  H01L31/02363 ,  H01L31/0682 ,  H01L31/1804 ,  H01L31/1864 ,  H01L31/1868 ,  H01L33/44 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/50

Abstract: Provided is a solar cell and a photovoltaic module. The solar cell includes a silicon substrate, and the silicon substrate includes a front surface and a back surface arranged opposite to each other. P-type conductive regions and N-type conductive regions are alternately arranged on the back surface of the silicon substrate. Front surface field regions are located on the front surface of the silicon substrate and spaced from each other. The front surface field regions each corresponds to one of the P-type conductive regions or one of the N-type conductive regions. At least one front passivation layer is located on the front surface of the silicon substrate. At least one back passivation layer is located on surfaces of the P-type conductive regions and N-type conductive regions.

公开(公告)号：US11908957B2

公开(公告)日：2024-02-20

申请号：US14622034

申请日：2015-02-13

Applicant: Shangrao Xinyuan YueDong Technology Development Co. Ltd

Inventor： Taeki Woo

IPC: H01L31/02 ,  H01L31/05 ,  H01L31/068

CPC classification number: H01L31/0201 ,  H01L31/0516 ,  H01L31/0682 ,  Y02E10/547

Abstract: A solar cell module includes first and second solar cells each including a plurality of first and second electrodes formed on a back surface of a semiconductor substrate, a first conductive line connected to the first electrodes, and a second conductive line connected to the second electrodes, and an interconnector connecting the first conductive line of the first solar cell to the second conductive line of the second solar cell. At least one of an area of an overlap portion, an area of a connection portion, a connection position, and a connection shape between the interconnector and the first conductive line of the first solar cell is different from at least one of an area of an overlap portion, an area of a connection portion, a connection position, and a connection shape between the interconnector and the second conductive line of the second solar cell.

公开(公告)号：US20240014329A1

公开(公告)日：2024-01-11

申请号：US18035094

申请日：2021-02-02

Applicant: CHINT NEW ENERGY TECHNOLOGY CO., LTD.

Inventor： Hongbo LI ,  Sheng HE ,  Wei SHAN ,  Wei-Chih HSU ,  Xinlin ZENG ,  Yingcai ZHAO

IPC: H01L31/0216 ,  H01L31/068

CPC classification number: H01L31/02167 ,  H01L31/0682

Abstract: Some embodiments of the present disclosure provide a back structure of a solar cell. The back structure includes an aluminum oxide film layer disposed on a silicon wafer substrate, and a first silicon nitride film layer and a first silicon oxynitride film layer, which are successively disposed on the aluminum oxide film layer from inside to outside; and the back structure further includes a second silicon nitride film layer disposed on the first silicon oxynitride film layer. The refractive index of the first silicon nitride film layer is greater than that of the second silicon nitride film layer, and the refractive index of the second silicon nitride film layer is greater than that of the first silicon oxynitride film layer.

公开(公告)号：US20230411543A1

公开(公告)日：2023-12-21

申请号：US17872035

申请日：2022-07-25

Applicant: ZHEJIANG JINKO SOLAR CO., LTD. ,  JINKO SOLAR CO., LTD.

Inventor： Huimin LI ,  Menglei XU ,  Jie YANG ,  Xinyu ZHANG

IPC: H01L31/0236 ,  H01L31/0216 ,  H01L31/0352 ,  H01L31/0368 ,  H01L31/05 ,  H01L31/068

CPC classification number: H01L31/02366 ,  H01L31/02168 ,  H01L31/03529 ,  H01L31/03682 ,  H01L31/0516 ,  H01L31/0682

Abstract: A semiconductor substrate, including a back surface having N-type conductive regions and P-type conductive regions. The N-type conductive regions are provided with first non-pyramidal texture structures, and the P-type conductive regions are provided with second non-pyramidal texture structures. A top surface of the first non-pyramidal texture structure is a polygonal plane, and a top surface of the second non-pyramidal texture structure is a polygonal plane. A one-dimensional size of the top surface of the first non-pyramidal texture structure is less than a one-dimensional size of the top surface of the second non-pyramidal texture structure. The one-dimensional size of the top surface of the first non-pyramidal texture structure is in a range of 5 μm to 12 μm. The one-dimensional size of the top surface of the second non-pyramidal texture structure is in a range of 10 μm to 40 μm.

公开(公告)号：US20230402553A1

公开(公告)日：2023-12-14

申请号：US17866217

申请日：2022-07-15

Applicant: ZHEJIANG JINKO SOLAR CO., LTD. ,  JINKO SOLAR CO., LTD.

Inventor： Kongsong CHEN ,  Menglei XU ,  Jie YANG ,  Xinyu ZHANG

IPC: H01L31/0216

CPC classification number: H01L31/02168 ,  H01L31/0682

Abstract: A solar cell includes: a substrate having front and back surfaces opposite to each other, the back surface includes first regions, second regions and gap regions, the first regions and the second regions are staggered and spaced from each other in a first direction, and each gap region is provided between one first region and one adjacent second region; a first conductive layer formed over the first region; a second conductive layer formed over the second region, the second conductive layer has a conductivity type opposite to the first conductive layer; a first electrode forming electrical contact with the first conductive layer; a second electrode forming electrical contact with the second conductive layer; and first pyramidal texture structures formed on the back surface corresponding to the gap regions. A curved interface region is formed between side wall of the first/second conductive layer and side wall of the adjacent gap region.