公开(公告)号：US09660615B2

公开(公告)日：2017-05-23

申请号：US14608723

申请日：2015-01-29

Applicant: MediaTek Inc.

Inventor： Meng-Cheng Peng ,  Rei-Fu Huang

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372

Abstract: A flip-flop device is provided. The flip-flop device includes a first flip-flop and a clock controller. The first flip-flop receives a first clock signal and a second clock signal for operation. The clock controller receives a clock source signal and generates the first clock signal and the second clock signal according to the clock source signal. Each of the first clock signal and the second clock signal switches between a first voltage level and a second voltage level. For each of the first clock signal and the second clock signal, a period of the first voltage level is shorter than a period of the second voltage level. The period of the first voltage level of the first clock signal and the period of the first voltage level of the second clock signal are non-overlapping.

公开(公告)号：US09659606B2

公开(公告)日：2017-05-23

申请号：US14634898

申请日：2015-03-02

Applicant: MEDIATEK INC.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/02 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

公开(公告)号：US20140104914A1

公开(公告)日：2014-04-17

申请号：US14043852

申请日：2013-10-02

Applicant: MEDIATEK INC.

Inventor： Rei-Fu Huang ,  Hang-Kaung Shu

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C29/848

Abstract: A content addressable memory (CAM) has a CAM array, a path selection circuit and a control circuit. The CAM array has a plurality of main columns of CAM cells and at least one redundant column of CAM cells. The path selection circuit receives an input search data, and outputs a plurality of bits of the input search data to a plurality of selected columns in the CAM array, respectively. The control circuit controls the path selection circuit to couple to the selected columns, and sets each CAM cell of at least one faulty column found in the main columns at a match state. The at least one faulty column is not included in the selected columns, and the at least one redundant column is included in the selected columns.

Abstract translation: 内容可寻址存储器（CAM）具有CAM阵列，路径选择电路和控制电路。 CAM阵列具有CAM单元的多个主列和至少一个CAM单元冗余列。 路径选择电路接收输入搜索数据，并将输入的搜索数据的多个比特分别输出到CAM阵列中的多个选择的列。 控制电路控制路径选择电路耦合到所选择的列，并将主列中发现的至少一个故障列的每个CAM单元设置为匹配状态。 所选择的列中不包括至少一个故障列，并且至少一个冗余列被包括在所选择的列中。

公开(公告)号：US10325634B2

公开(公告)日：2019-06-18

申请号：US15441480

申请日：2017-02-24

Applicant: MediaTek Inc.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/12 ,  G11C7/14 ,  G11C7/08 ,  G11C7/22 ,  G11C7/06

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

公开(公告)号：US20170169868A1

公开(公告)日：2017-06-15

申请号：US15441480

申请日：2017-02-24

Applicant: MediaTek Inc.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/12 ,  G11C7/14 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

公开(公告)号：US09876488B2

公开(公告)日：2018-01-23

申请号：US15250546

申请日：2016-08-29

Applicant: MediaTek Inc.

Inventor： Rei-Fu Huang

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/35606 ,  H03K3/012

Abstract: A flip-flop circuit includes a D flip-flop and a gating controller. The D flip-flop generates an output signal according to a data signal and a gated clock signal. The gating controller receives an original clock signal. The gating controller further compares the output signal with the data signal. If the output signal is the same as the data signal, the gating controller will maintain the gated clock signal at a constant logic level. If the output signal is different from the data signal, the gating controller will use the original clock signal as the gated clock signal.

公开(公告)号：US20160180894A1

公开(公告)日：2016-06-23

申请号：US14634898

申请日：2015-03-02

Applicant: Mediatek Inc.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/08 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

Abstract translation: 本发明公开了一种具有用于单端位线存储器的动态参考电压的差分感测电路。 示例性差分感测电路包括：动态电压基准产生单元和差分感测放大单元。 动态电压基准产生单元耦合到输入电压，并用于接收设置信号以产生动态电压基准。 差分感测放大单元耦合到单端位线存储器和动态电压基准产生单元，用于至少从单端位线存储器接收输入信号和从动态参考电压源接收动态参考电压 生成单元，以便相应地产生至少一个输出信号。

公开(公告)号：US09013907B2

公开(公告)日：2015-04-21

申请号：US14043852

申请日：2013-10-02

Applicant: Mediatek Inc.

Inventor： Rei-Fu Huang ,  Hang-Kaung Shu

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C29/848

Abstract: A content addressable memory (CAM) has a CAM array, a path selection circuit and a control circuit. The CAM array has a plurality of main columns of CAM cells and at least one redundant column of CAM cells. The path selection circuit receives an input search data, and outputs a plurality of bits of the input search data to a plurality of selected columns in the CAM array, respectively. The control circuit controls the path selection circuit to couple to the selected columns, and sets each CAM cell of at least one faulty column found in the main columns at a match state. The at least one faulty column is not included in the selected columns, and the at least one redundant column is included in the selected columns.

Abstract translation: 内容可寻址存储器（CAM）具有CAM阵列，路径选择电路和控制电路。 CAM阵列具有CAM单元的多个主列和至少一个CAM单元冗余列。 路径选择电路接收输入搜索数据，并将输入的搜索数据的多个比特分别输出到CAM阵列中的多个选择的列。 控制电路控制路径选择电路耦合到所选择的列，并将主列中发现的至少一个故障列的每个CAM单元设置为匹配状态。 所选择的列中不包括至少一个故障列，并且至少一个冗余列被包括在所选择的列中。

公开(公告)号：US09948282B2

公开(公告)日：2018-04-17

申请号：US14922405

申请日：2015-10-26

Applicant: MediaTek Inc.

Inventor： Rei-Fu Huang

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375

Abstract: A retention flip-flop is provided. The flip-flop includes a clock generation circuit, a master latch circuit, and a salve latch circuit. The clock generation circuit generates first and second clock signals in a first mode. The master latch circuit performs a first latch operation on an input signal from the input terminal according to the first and second clock signals to generate a first latched signal at a first node in the first mode. The salve latch circuit performs a second latch operation on the first latched signal according to the first and second clock signals to generate a second latched signal at a second node in the first mode. In a sleep or power-down mode, the total number of transistors in the clock generation circuit and the salve latch circuit is equal to or less than eight.

公开(公告)号：US09653186B2

公开(公告)日：2017-05-16

申请号：US14600496

申请日：2015-01-20

Applicant: MediaTek Inc.

Inventor： Chin-Jung Su ,  Rei-Fu Huang

IPC: G11C29/00 ,  G11C29/56 ,  G11C29/12

CPC classification number: G11C29/56012 ,  G11C29/12015

Abstract: A memory-testing device for testing a memory is provided. The memory-testing device includes a testing circuitry and a register. The testing circuitry is coupled to the memory for testing performance of the memory. The register is coupled to the testing circuitry and inputted by a testing clock signal, wherein the testing clock signal is different from an original clock signal of the memory and/or the testing circuitry. The testing clock signal is utilized for adjusting the time when the memory-testing device latches data from the memory to decrease a timing slack of the memory-testing device.