公开(公告)号：US20160141020A1

公开(公告)日：2016-05-19

申请号：US14543910

申请日：2014-11-18

Applicant: MEDIATEK INC.

Inventor： Rei-Fu Huang ,  Shih-Huang Huang

IPC: G11C11/418 ,  G11C29/00 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/41 ,  G11C11/419 ,  G11C29/10 ,  G11C2029/1202 ,  G11C2029/5002

Abstract: A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively. The row decoder is arranged to assert one of the memory cell rows according to a row address. The plurality of word-line drivers are each coupled to the row decoder and one of the memory cell rows. The arbiter is arranged to prevent multiple memory cells at a same word-line from being accessed at a same time.

Abstract translation: 静态随机存取存储器（SRAM）包括存储单元阵列，行解码器，多个字线驱动器和仲裁器。 存储单元阵列包括多个存储单元行，其中存储单元行分别由多个字线使能。 行解码器被布置为根据行地址来声明其中一个存储单元行。 多个字线驱动器各自耦合到行解码器和存储单元行之一。 仲裁器被布置成防止同一字线上的多个存储器单元被同时访问。

公开(公告)号：US20160180894A1

公开(公告)日：2016-06-23

申请号：US14634898

申请日：2015-03-02

Applicant: Mediatek Inc.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/08 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

Abstract translation: 本发明公开了一种具有用于单端位线存储器的动态参考电压的差分感测电路。 示例性差分感测电路包括：动态电压基准产生单元和差分感测放大单元。 动态电压基准产生单元耦合到输入电压，并用于接收设置信号以产生动态电压基准。 差分感测放大单元耦合到单端位线存储器和动态电压基准产生单元，用于至少从单端位线存储器接收输入信号和从动态参考电压源接收动态参考电压 生成单元，以便相应地产生至少一个输出信号。

公开(公告)号：US10325634B2

公开(公告)日：2019-06-18

申请号：US15441480

申请日：2017-02-24

Applicant: MediaTek Inc.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/12 ,  G11C7/14 ,  G11C7/08 ,  G11C7/22 ,  G11C7/06

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

公开(公告)号：US20170169868A1

公开(公告)日：2017-06-15

申请号：US15441480

申请日：2017-02-24

Applicant: MediaTek Inc.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/12 ,  G11C7/14 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

公开(公告)号：US10043578B2

公开(公告)日：2018-08-07

申请号：US15345806

申请日：2016-11-08

Applicant: MEDIATEK INC.

Inventor： Shu-Lin Lai ,  Shu-Hsuan Lin ,  Shih-Huang Huang

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/06

Abstract: A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

公开(公告)号：US09659606B2

公开(公告)日：2017-05-23

申请号：US14634898

申请日：2015-03-02

Applicant: MEDIATEK INC.

Inventor： Shih-Huang Huang ,  Rei-Fu Huang

IPC: G11C7/02 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22

Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.

公开(公告)号：US09449680B2

公开(公告)日：2016-09-20

申请号：US14692126

申请日：2015-04-21

Applicant: MediaTek Inc.

Inventor： Shih-Huang Huang

IPC: G11C5/06 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A write assist circuit capable of writing data to a memory cell with a bit line and a bit line bar is provided. The write assist circuit includes a clamping circuit, and first and second sense amplifiers. The clamping circuit is coupled to first and second nodes to prevent the voltage of the first and second nodes from being lower than a data-retention voltage. The first and second nodes are supplied with first and second voltage sources. The first and second sense amplifier are utilized to detect the voltage of the bit line or the bit line bar, amplify the voltage and pull down the voltage of one of the first or second node according to the data while the voltage of the other one of the first or second node is kept at a power supply voltage level.

Abstract translation: 提供一种能够用位线和位线条将数据写入存储单元的写辅助电路。 写辅助电路包括钳位电路以及第一和第二读出放大器。 钳位电路耦合到第一和第二节点，以防止第一和第二节点的电压低于数据保持电压。 第一和第二节点被提供有第一和第二电压源。 第一和第二读出放大器被用于检测位线或位线条的电压，放大电压并根据数据降低第一或第二节点之一的电压，而另一个的电压 第一或第二节点保持在电源电压电平。

公开(公告)号：US08879304B2

公开(公告)日：2014-11-04

申请号：US14020323

申请日：2013-09-06

Applicant: MediaTek Inc.

Inventor： Shih-Huang Huang

IPC: G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C5/14 ,  G11C8/08 ,  G11C7/20

CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C7/20 ,  G11C8/08 ,  G11C11/418 ,  G11C2207/2227

Abstract: A word line control circuit includes a first PMOS transistor having a gate coupled to a first selection signal; a first NMOS transistor, coupled between a second node and a second voltage terminal, having a gate coupled to an inverted first selection signal, wherein the inverted first selection signal is obtained by inverting the first selection signal; and a plurality of word line drivers, at least one of the word line drivers comprising a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first voltage terminal, a negative power terminal of the first inverter is coupled to the second node, a positive power terminal of the second inverter is coupled to the first node, and a negative power terminal of the second inverter is coupled to the second voltage terminal.

Abstract translation: 字线控制电路包括具有耦合到第一选择信号的栅极的第一PMOS晶体管; 耦合在第二节点和第二电压端子之间的第一NMOS晶体管，具有耦合到反相第一选择信号的栅极，其中反相第一选择信号通过反相第一选择信号而获得; 以及多个字线驱动器，所述字线驱动器中的至少一个包括第一反相器和第二反相器，其中所述第一反相器的正电源端子耦合到所述第一电压端子，所述第一反相器的负电源端子 耦合到第二节点，第二反相器的正电源端子耦合到第一节点，并且第二反相器的负电源端子耦合到第二电压端子。