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公开(公告)号:US20140052889A1
公开(公告)日:2014-02-20
申请号:US13968504
申请日:2013-08-16
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
IPC分类号: G06F13/40
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明涉及一种具有耦合在上游结构和集成设备结构之间的虚拟端口的集成端点,该虚拟端口包括多功能逻辑,以处理与一个或多个知识产权(IP) 集成设备结构。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。 描述和要求保护其他实施例。
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公开(公告)号:US08831029B2
公开(公告)日:2014-09-09
申请号:US13025312
申请日:2011-02-11
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
IPC分类号: H04L12/66 , G06F15/16 , G06F13/40 , H04L12/64 , H04L12/18 , H04L12/40 , G06F13/42 , G06F13/10 , H04L29/08
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: An integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric is disclosed. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic.
摘要翻译: 公开了一种集成端点,其具有耦合在上游结构和集成设备结构之间的虚拟端口,该虚拟端口包括用于处理耦合到集成设备结构的一个或多个知识产权(IP)块的各种功能的多功能逻辑。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。
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公开(公告)号:US20110080920A1
公开(公告)日:2011-04-07
申请号:US12965553
申请日:2010-12-10
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
IPC分类号: H04L12/56
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
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公开(公告)号:US20100246594A1
公开(公告)日:2010-09-30
申请号:US12415470
申请日:2009-03-31
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
IPC分类号: H04L12/56
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明涉及一种具有耦合在上游结构和集成设备结构之间的虚拟端口的集成端点,该虚拟端口包括多功能逻辑,以处理与一个或多个知识产权(IP) 集成设备结构。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。 描述和要求保护其他实施例。
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公开(公告)号:US08537848B2
公开(公告)日:2013-09-17
申请号:US12965553
申请日:2010-12-10
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
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公开(公告)号:US08537820B2
公开(公告)日:2013-09-17
申请号:US13025319
申请日:2011-02-11
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
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公开(公告)号:US07873068B2
公开(公告)日:2011-01-18
申请号:US12415470
申请日:2009-03-31
申请人: Michael Klinglesmith , Mohan Nair , Joseph Murray
发明人: Michael Klinglesmith , Mohan Nair , Joseph Murray
CPC分类号: G06F13/4027 , G06F13/105 , G06F13/4221 , G06F2213/0026 , H04L12/1845 , H04L12/40032 , H04L12/6418 , H04L29/08468 , H04L67/1078
摘要: An integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic.
摘要翻译: 集成端点,其具有耦合在上游结构和集成设备结构之间的虚拟端口,该虚拟端口包括用于处理耦合到集成设备结构的一个或多个知识产权(IP)块的各种功能的多功能逻辑。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。
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公开(公告)号:US20140281616A1
公开(公告)日:2014-09-18
申请号:US13799524
申请日:2013-03-13
申请人: Douglas Moran , Achmed Rumi Zahir , William Knolla , Hartej Singh , Vasudev Vasu Bibikar , Sanjeev Jahagirdar , Michael Klinglesmith , Irwin Vaz , Varghese George
发明人: Douglas Moran , Achmed Rumi Zahir , William Knolla , Hartej Singh , Vasudev Vasu Bibikar , Sanjeev Jahagirdar , Michael Klinglesmith , Irwin Vaz , Varghese George
IPC分类号: G06F1/32
CPC分类号: G06F1/3234 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,处理器包括至少一个功能块和中央功率控制器。 至少一个功能块可以包括至少一个块组件和块功率逻辑。 块功率逻辑可以是:接收在所述至少一个功能块中发起第一降低功率模式的第一请求,并且响应于所述第一请求,向中央功率控制器发送通知信号。 中央功率控制器可以响应于通知信号:存储至少一个功能块的第一状态,并且启动至少一个功能块中的第一降低功率模式。 描述和要求保护其他实施例。
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