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公开(公告)号：US20120289167A1
公开(公告)日：2012-11-15
申请号：US13464879
申请日：2012-05-04
CPC分类号： H04B17/0085 , G01R31/2822
摘要： A system for testing and calibrating communications equipment or modules. A processor is configured to perform a test or calibration procedure on a communications unit under test (UUT) in response to commands entered by an operator. Test and measurement instruments arranged to be responsive to the computer include a power supply for activating selected portions of signal paths in the UUT, one or more signal generators, and one or more instruments for measuring output signals produced by the UUT in response to the test signals. The UUT has switches and terminals for inputting test signals from and returning output signals to the instruments, and an adapter is connected between the processor and the UUT. When performing a calibration procedure, the adapter operates the switches and connects the terminals on the UUT to the test and measurement instruments under the control of the processor.
摘要翻译： 用于测试和校准通信设备或模块的系统。 处理器被配置为响应于操作者输入的命令在被测通信单元（UUT）上执行测试或校准过程。 布置为响应于计算机的测试和测量仪器包括用于激活UUT中的信号路径的选定部分的一个电源，一个或多个信号发生器，以及用于测量由UUT响应于测试而产生的输出信号的一个或多个仪器 信号。 UUT具有用于从仪器输入测试信号和返回输出信号的开关和端子，并且适配器连接在处理器和UUT之间。 当执行校准程序时，适配器操作开关，并将UUT上的端子连接到处理器控制下的测试和测量仪器。
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2.发明授权System for testing and calibrating core engine radio frequency (RF) circuit card assemblies 有权核心引擎射频（RF）电路卡组件的测试和校准系统公开(公告)号：US09065559B2
公开(公告)日：2015-06-23
申请号：US13464879
申请日：2012-05-04
CPC分类号： H04B17/0085 , G01R31/2822
摘要： A system for testing and calibrating communications equipment or modules. A processor is configured to perform a test or calibration procedure on a communications unit under test (UUT) in response to commands entered by an operator. Test and measurement instruments arranged to be responsive to the computer include a power supply for activating selected portions of signal paths in the UUT, one or more signal generators, and one or more instruments for measuring output signals produced by the UUT in response to the test signals. The UUT has switches and terminals for inputting test signals from and returning output signals to the instruments, and an adapter is connected between the processor and the UUT. When performing a calibration procedure, the adapter operates the switches and connects the terminals on the UUT to the test and measurement instruments under the control of the processor.
摘要翻译： 用于测试和校准通信设备或模块的系统。 处理器被配置为响应于操作者输入的命令在被测通信单元（UUT）上执行测试或校准过程。 布置为响应于计算机的测试和测量仪器包括用于激活UUT中的信号路径的选定部分的一个电源，一个或多个信号发生器，以及用于测量由UUT响应于测试而产生的输出信号的一个或多个仪器 信号。 UUT具有用于从仪器输入测试信号和返回输出信号的开关和端子，并且适配器连接在处理器和UUT之间。 当执行校准程序时，适配器操作开关，并将UUT上的端子连接到处理器控制下的测试和测量仪器。
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公开(公告)号：US08838058B2
公开(公告)日：2014-09-16
申请号：US13465977
申请日：2012-05-07
申请人： Michael S. Vogas
发明人： Michael S. Vogas
CPC分类号： H04B1/40
摘要： A communications radio or transceiver having an extended upper operating frequency limit of at least 6 GHz. The radio includes a first IF conversion stage for receiving and downconverting a RF input signal to a first IF signal, and a second IF conversion stage for downconverting the first IF signal to a second IF signal. The first and the second conversion stages each have adjustable first and second attenuators, a serial peripheral interface (SPI) for controlling the attenuators in response to command words, a mixer coupled to an output of the second attenuator, and a buffer for applying a local oscillator (LO) signal to an input of the mixer. Each conversion stage is in the form of an integrated circuit chip. Component devices of each chip and electrical connections between the components, are dimensioned so that the chip has a 6 GHz upper frequency limit.
摘要翻译： 具有至少6GHz的上限工作频率限制的通信无线电或收发器。 无线电装置包括用于接收和下变频RF输入信号到第一IF信号的第一IF转换级，以及用于将第一IF信号下变频到第二IF信号的第二IF转换级。 第一和第二转换级各自具有可调节的第一和第二衰减器，用于响应命令字控制衰减器的串行外围接口（SPI），耦合到第二衰减器的输出的混频器，以及用于施加本地 振荡器（LO）信号到混频器的输入端。 每个转换阶段都是集成电路芯片的形式。 每个芯片的组件设备和组件之间的电气连接的尺寸使得芯片具有6GHz的上限频率。
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公开(公告)号：US20120289171A1
公开(公告)日：2012-11-15
申请号：US13465977
申请日：2012-05-07
申请人： Michael S. Vogas
发明人： Michael S. Vogas
CPC分类号： H04B1/40
摘要： A communications radio or transceiver having an extended upper operating frequency limit of at least 6 GHz. The radio includes a first IF conversion stage for receiving and downconverting a RF input signal to a first IF signal, and a second IF conversion stage for downconverting the first IF signal to a second IF signal. The first and the second conversion stages each have adjustable first and second attenuators, a serial peripheral interface (SPI) for controlling the attenuators in response to command words, a mixer coupled to an output of the second attenuator, and a buffer for applying a local oscillator (LO) signal to an input of the mixer. Each conversion stage is in the form of an integrated circuit chip. Component devices of each chip and electrical connections between the components, are dimensioned so that the chip has a 6 GHz upper frequency limit.
摘要翻译： 具有至少6GHz的上限工作频率限制的通信无线电或收发器。 无线电装置包括用于接收和下变频RF输入信号到第一IF信号的第一IF转换级，以及用于将第一IF信号下变频到第二IF信号的第二IF转换级。 第一和第二转换级各自具有可调节的第一和第二衰减器，用于响应命令字控制衰减器的串行外围接口（SPI），耦合到第二衰减器的输出的混频器，以及用于施加本地 振荡器（LO）信号到混频器的输入端。 每个转换阶段都是集成电路芯片的形式。 每个芯片的组件设备和组件之间的电气连接的尺寸使得芯片具有6GHz的上限频率。
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5.发明申请CLOCK DISTRIBUTION ARCHITECTURE FOR DUAL INTEGRATED CORE ENGINE TRANSCEIVER FOR USE IN RADIO SYSTEM 有权用于无线电系统的双集成核心发射机收发器的时钟分配架构公开(公告)号：US20120287977A1
公开(公告)日：2012-11-15
申请号：US13465269
申请日：2012-05-07
申请人： Boris Radovcic , Michael S. Vogas
发明人： Boris Radovcic , Michael S. Vogas
CPC分类号： H04L7/0008
摘要： A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.
摘要翻译： 公开了一种将参考时钟的损坏最小化到无线电系统中的RF电路的方法和装置。 DICE-T以GVA的低电压差分信号（LVDS）格式接收参考时钟。 DICE-T个性卡将参考时钟信号转换为模拟信号。 模拟信号提供给核心引擎RF卡，并将LVDS格式信号提供给核心引擎调制解调器进行本地时钟。 核心引擎RF将模拟信号馈送到可编程锁相环芯片中，以产生RF处理所需的所有时钟。 模拟信号也用于向核心引擎调制解调器的ADC和DAC提供时钟。 通过将参考时钟直接路由到RF卡，然后导出调制解调器时钟，降低了参考时钟的相位噪声。
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6.发明申请公开(公告)号：US20120289175A1
公开(公告)日：2012-11-15
申请号：US13455745
申请日：2012-04-25
申请人： Michael S. Vogas
发明人： Michael S. Vogas
IPC分类号： H04B17/00
CPC分类号： H04B7/0617
摘要： A method of controlling the phases of RF output signals from a number of radio transmitters. A given radio has at least one synthesizer as a source of its RF output signal, and the synthesizer produces an output the phase offset of which relative to a reference signal is controlled by a phase offset command. A path from an antenna port of the radio obtains a fed back RF output signal and a phase difference between the reference signal and the fed back RF output signal is measured. A value of a zero degree phase offset command for the synthesizer is determined such that the phase difference between the reference signal and the fed back RF signal is nominally zero, and the value is stored. A phase offset command for providing a desired phase offset for the RF output signal is then determined based the stored value of the zero degree phase offset command.
摘要翻译： 一种控制来自多个无线电发射机的RF输出信号的相位的方法。 给定无线电具有至少一个合成器作为其RF输出信号的源，并且合成器产生相对于参考信号的相位偏移由相位偏移指令控制的输出。 来自无线电天线端口的路径获得反馈RF输出信号，并且测量参考信号和反馈RF输出信号之间的相位差。 确定用于合成器的零度相位偏移指令的值，使得参考信号和反馈RF信号之间的相位差额定为零，并且存储该值。 然后，基于零度相位偏移指令的存储值来确定用于为RF输出信号提供期望的相位偏移的相位偏移指令。
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公开(公告)号：US20120287585A1
公开(公告)日：2012-11-15
申请号：US13466990
申请日：2012-05-08
申请人： Michael S. Vogas , Boris Radovcic , Todd R. DeLuck , George M. Horihan , Minh Le , Kenneth Kolodziej
发明人： Michael S. Vogas , Boris Radovcic , Todd R. DeLuck , George M. Horihan , Minh Le , Kenneth Kolodziej
IPC分类号： H05K1/14
CPC分类号： H05K1/144 , H05K2201/09027 , H05K2201/10098 , H05K2201/10189
摘要： A compact communications radio core engine (CE) module includes a modem circuit board having a first connector, and a radio frequency (RF) circuit board having a second connector configured to mate with the first connector of the modem circuit card. A module shell is constructed and arranged to contain the modem and the RF circuit boards in such an orientation so that the second connector of the RF circuit board can operatively engage the first connector of the modem circuit card.
摘要翻译： 紧凑型通信无线电核心引擎（CE）模块包括具有第一连接器的调制解调器电路板和具有被配置为与调制解调器电路卡的第一连接器配合的第二连接器的射频（RF）电路板。 模块壳被构造和布置成将调制解调器和RF电路板以这样的方向容纳，使得RF电路板的第二连接器可操作地接合调制解调器电路卡的第一连接器。
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8.发明申请公开(公告)号：US20120286894A1
公开(公告)日：2012-11-15
申请号：US13451318
申请日：2012-04-19
申请人： Michael S. Vogas
发明人： Michael S. Vogas
CPC分类号： H03H9/0542 , H03H9/0557 , H03H2240/00
摘要： A filter package for communications equipment includes two or more filters in die form, each having a different frequency response. A first switch and a second switch are operatively connected to the filters and are configured to select a desired filter for operation in a signal stage of the equipment. The filters are aligned and stacked one over the other in the form of a package having an input terminal that is tied to a common terminal of the first switch, and an output terminal tied to a common terminal of the second switch. When the input and the output terminals of the filter package are connected to corresponding terminals of an intermediate frequency (IF) stage in a communications transceiver, the package can support both narrowband and wideband waveforms defined by the Joint Tactical Radio System (JTRS).
摘要翻译： 用于通信设备的滤波器组件包括两个或更多个芯片形式的滤波器，每个滤波器具有不同的频率响应。 第一开关和第二开关可操作地连接到滤波器并且被配置为选择期望的滤波器以在设备的信号级中操作。 滤波器以具有连接到第一开关的公共端子的输入端子的封装的形式彼此对准和堆叠，以及连接到第二开关的公共端子的输出端子。 当滤波器封装的输入和输出端连接到通信收发器中的中频（IF）级的相应端时，封装可以支持由联合战术无线电系统（JTRS）定义的窄带和宽带波形。
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9.发明授权Tactical radio transceiver with intermediate frequency (IF) filter package for narrowband and wideband signal waveforms 有权具有中频（IF）滤波器封装的战术无线电收发器，用于窄带和宽带信号波形公开(公告)号：US08954025B2
公开(公告)日：2015-02-10
申请号：US13450237
申请日：2012-04-18
申请人： Michael S. Vogas
发明人： Michael S. Vogas
CPC分类号： H03H9/0557 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H03H9/0542 , H03H2240/00 , H04B1/006 , H01L2924/00
摘要： A communications radio has an IF stage with an associated filter array. The array includes at least one narrowband filter whose passband is less than 3 MHz, at least one wideband filter whose passband is 3 MHz or greater, a first switch with a common pole connected to an input terminal of the array, a second switch with a common pole connected to an output terminal of the array, a third switch whose common pole is operatively connected to the input terminal, and a fourth switch whose common pole is operatively connected to the output terminal. The first and the second switches cooperate to insert a selected filter between the first and second terminals. The third and the fourth switches cooperate to insert the filter array into either a receive signal path when the radio is in a receive mode, or a transmit signal path when in a transmit mode.
摘要翻译： 通信无线电装置具有具有相关联的滤波器阵列的IF级。 该阵列包括通带小于3MHz的至少一个窄带滤波器，通带为3MHz或更大的至少一个宽带滤波器，具有连接到阵列的输入端的公共极的第一开关，具有 公共极连接到阵列的输出端，第三开关，其公共极可操作地连接到输入端;以及第四开关，其公共极可操作地连接到输出端。 第一和第二开关协作以在第一和第二端子之间插入选定的过滤器。 当无线电处于接收模式时，第三和第四交换机协作将滤波器阵列插入到接收信号路径中，或者当处于发送模式时将发送信号路径插入到接收信号路径中。
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10.发明授权Clock distribution architecture for dual integrated core engine transceiver for use in radio system 有权用于无线电系统的双集成核心引擎收发器的时钟分配架构公开(公告)号：US08929422B2
公开(公告)日：2015-01-06
申请号：US13465269
申请日：2012-05-07
申请人： Boris Radovcic , Michael S. Vogas
发明人： Boris Radovcic , Michael S. Vogas
CPC分类号： H04L7/0008
摘要： A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.
摘要翻译： 公开了一种将参考时钟的损坏最小化到无线电系统中的RF电路的方法和装置。 DICE-T以GVA的低电压差分信号（LVDS）格式接收参考时钟。 DICE-T个性卡将参考时钟信号转换为模拟信号。 模拟信号提供给核心引擎RF卡，并将LVDS格式信号提供给核心引擎调制解调器进行本地时钟。 核心引擎RF将模拟信号馈送到可编程锁相环芯片中，以产生RF处理所需的所有时钟。 模拟信号也用于向核心引擎调制解调器的ADC和DAC提供时钟。 通过将参考时钟直接路由到RF卡，然后导出调制解调器时钟，降低了参考时钟的相位噪声。
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