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公开(公告)号：US20100013692A1
公开(公告)日：2010-01-21
申请号：US12377989
申请日：2007-08-10
IPC分类号： H03M1/34
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock.A clock generator circuit (104) for automatically generating an operation clock is provided inside an A/D converter (100) to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译： 操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。 在A / D转换器（100）内部设置用于自动生成操作时钟的时钟发生器电路（104），使得A / D转换器不需要外部输入操作时钟。 此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。
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公开(公告)号：US07986256B2
公开(公告)日：2011-07-26
申请号：US12377989
申请日：2007-08-10
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/365
摘要： An external input operation clock signal is required for operating a conventional A/D converter, and the performance of the A/D converter is undesirably determined by the characteristics of the external input operation clock. A clock generator circuit for automatically generating an operation clock is provided inside an A/D converter to make the A/D converter require no external input operation clock. Further, a circuit for detecting the operation times of the constituents of the A/D converter is provided to generate a clock with which the A/D converter is optimally operated, thereby realizing high-speed operation and low power consumption.
摘要翻译： 操作常规A / D转换器需要外部输入操作时钟信号，并且A / D转换器的性能不合需要地由外部输入操作时钟的特性决定。 在A / D转换器内部设置用于自动生成工作时钟的时钟发生器电路，使A / D转换器不需要外部输入操作时钟。 此外，提供用于检测A / D转换器的组成部分的操作时间的电路，以产生A / D转换器被最佳操作的时钟，从而实现高速操作和低功耗。
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公开(公告)号：US20100007541A1
公开(公告)日：2010-01-14
申请号：US12439444
申请日：2007-08-10
申请人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
发明人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
IPC分类号： H03M1/34
CPC分类号： H03M1/0624 , H03M1/206 , H03M1/365
摘要： The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.
摘要翻译： 传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。
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公开(公告)号：US07834794B2
公开(公告)日：2010-11-16
申请号：US12439444
申请日：2007-08-10
申请人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
发明人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
IPC分类号： H03M1/12
CPC分类号： H03M1/0624 , H03M1/206 , H03M1/365
摘要： The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.
摘要翻译： 传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。
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公开(公告)号：US08487802B2
公开(公告)日：2013-07-16
申请号：US13052817
申请日：2011-03-21
申请人： Junichi Naka , Masakazu Shigemori
发明人： Junichi Naka , Masakazu Shigemori
IPC分类号： H03M1/34
CPC分类号： H03K5/249
摘要： Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.
摘要翻译： 降低功耗增加，运行速度提高。 比较器包括比较部分，其输出构成输入差分信号的第一电压和第二电压之间的比较结果，与第一时钟信号同步操作的第一正反馈部分，放大比较部分的结果， 并将放大的结果输出到输出节点对，以及与第二时钟信号同步工作的第二正反馈部分，并向输出节点对提供正反馈。
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公开(公告)号：US20110169681A1
公开(公告)日：2011-07-14
申请号：US13052817
申请日：2011-03-21
申请人： Junichi NAKA , Masakazu Shigemori
发明人： Junichi NAKA , Masakazu Shigemori
CPC分类号： H03K5/249
摘要： Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.
摘要翻译： 降低功耗增加，运行速度提高。 比较器包括比较部分，其输出构成输入差分信号的第一电压和第二电压之间的比较结果，与第一时钟信号同步操作的第一正反馈部分，放大比较部分的结果， 并将放大的结果输出到输出节点对，以及与第二时钟信号同步工作的第二正反馈部分，并向输出节点对提供正反馈。
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公开(公告)号：US20120044103A1
公开(公告)日：2012-02-23
申请号：US13287617
申请日：2011-11-02
IPC分类号： H03M1/36
摘要： A parallel interpolation A/D converter includes a reference voltage generation circuit configured to generate (m+1) different reference voltages VR1-VRm+1, where m is a positive integer, and VR1
摘要翻译： 并行内插A / D转换器包括：参考电压产生电路，被配置为产生（m + 1）不同的参考电压VR1-VRm + 1，其中m是正整数，VR1
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