公开(公告)号：US20090179787A1

公开(公告)日：2009-07-16

申请号：US12093565

申请日：2006-04-18

Applicant: Junichi Naka ,  Koji Sushihara

Inventor： Junichi Naka ,  Koji Sushihara

IPC: H03M1/12 ,  H03K5/22

CPC classification number: H03M1/0607 ,  H03K5/2481 ,  H03M1/204 ,  H03M1/362

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract translation: 一种用于并行型A / D转换器的比较器，其中比较器100包括复位晶体管mra和mrb。 当比较器100处于复位状态时，将时钟信号的反相信号/ CLK提供给PMOS复位晶体管mra和mrb，以便将两个作为差分对的内部节点Va和Vb的两个电压强制复位到 复位晶体管mra和mrb的预定复位电压。 以预定的延迟产生时钟信号的反相信号/ CLK。 因此，当比较器100处于复位状态时，消除内部节点Va和Vb的复位的时间点比比较器执行比较操作的时间延迟。 因此，即使时钟信号的频率和模拟输入信号的频率高，形成差分对的内部节点的电压在比较器处于复位状态时也是平衡的，从而提高电压比较精度 。

公开(公告)号：US07061419B2

公开(公告)日：2006-06-13

申请号：US11010423

申请日：2004-12-14

Applicant: Koji Sushihara ,  Takashi Morie

Inventor： Koji Sushihara ,  Takashi Morie

IPC: H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/0682 ,  H03M1/365

Abstract: In a flash A/D converter including a plurality of differential amplifier circuits and a plurality of voltage comparator circuits, a regulator circuit is provided. The regulator circuit automatically regulates a bias voltage of each of the plurality of differential amplifier circuits in a differential amplifier circuit array to make an output dynamic range for the differential amplifier circuits match an input dynamic range for the plurality of voltage comparator circuits. Therefore, even if the input dynamic range for the voltage comparator circuits is narrowed with reduction in a power supply voltage, the output dynamic range for the differential amplifier circuits and the input dynamic range for the voltage comparator circuits match, thus resulting in a high A/D conversion accuracy.

公开(公告)号：US07834794B2

公开(公告)日：2010-11-16

申请号：US12439444

申请日：2007-08-10

Applicant: Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

Inventor： Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

IPC: H03M1/12

CPC classification number: H03M1/0624 ,  H03M1/206 ,  H03M1/365

Abstract: The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

Abstract translation: 传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

公开(公告)号：US07898449B2

公开(公告)日：2011-03-01

申请号：US12562664

申请日：2009-09-18

Applicant: Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

Inventor： Shoji Kawahito ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC: H03M1/12

CPC classification number: H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract translation: 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个连接到两个共源共栅电路的辅助差分放大器，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US06252440B1

公开(公告)日：2001-06-26

申请号：US09445392

申请日：2000-03-07

Applicant: Koji Sushihara ,  Takashi Yamamoto ,  Kenichi Ishida

Inventor： Koji Sushihara ,  Takashi Yamamoto ,  Kenichi Ishida

IPC: H03K300

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B5/40

Abstract: In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

Abstract translation: 在用于切换通过具有电感分量的磁头等的写入电流的写入驱动电路中，通过使用四个NPN晶体管形成H形桥接电路，以便以高速切换写入电流 。 提供用于控制四个NPN晶体管的基极电位的四个开关装置，以及用于快速降低电源侧的两个NPN晶体管中的一个的基极电位的两个开关装置，当写入电流通过磁 提供头部切换，从而扩大在磁头的两个端子之间出现的电压差。

公开(公告)号：US5627490A

公开(公告)日：1997-05-06

申请号：US597258

申请日：1996-02-06

Applicant: Koji Sushihara ,  Takashi Yamamoto ,  Ikuo Imanishi ,  Tsuyoshi Nakamura ,  Michinori Kishimoto ,  Kenichi Ishida

Inventor： Koji Sushihara ,  Takashi Yamamoto ,  Ikuo Imanishi ,  Tsuyoshi Nakamura ,  Michinori Kishimoto ,  Kenichi Ishida

IPC: G05F3/26 ,  H03F1/48 ,  H03F3/42 ,  H03K3/45

CPC classification number: H03F3/42 ,  G05F3/265 ,  H03F1/48

Abstract: An amplifier circuit for amplifying a change in a resistance value of a magnetic resistance element is formed by connecting a first and a second current mirror circuits having the same structure in cascode, so that a voltage change is amplified without using a capacitive coupling. Hence, a high-pass filter is not created as a parasitic circuit, whereby a gain is maintained high in the low frequency region and a low frequency characteristic is excellent. Further, since control electrodes of transistors which form each current mirror circuit are grounded through the capacitance, a noise is reduced without using a conventional feedback circuit. This eliminates an influence of the feedback circuit over a high frequency characteristic, and therefore, a high frequency characteristic becomes excellent.

Abstract translation: 通过将具有相同结构的第一和第二电流镜电路串联连接形成用于放大电阻元件的电阻值变化的放大器电路，从而在不使用电容耦合的情况下放大电压变化。 因此，不产生高通滤波器作为寄生电路，从而在低频区域中增益保持较高，并且低频特性优异。 此外，由于形成每个电流镜电路的晶体管的控制电极通过电容接地，所以在不使用常规反馈电路的情况下，噪声降低。 这消除了反馈电路对高频特性的影响，因此高频特性变得优异。

公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

Applicant: Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

Inventor： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  G11C27/026 ,  H03M1/1215

Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Abstract translation: 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US20100073214A1

公开(公告)日：2010-03-25

申请号：US12562664

申请日：2009-09-18

Applicant: Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

Inventor： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC: H03M1/12 ,  H03F3/45

CPC classification number: H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract translation: 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个辅助差分放大器，其连接到两个共源共栅电路，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US20100007541A1

公开(公告)日：2010-01-14

申请号：US12439444

申请日：2007-08-10

Applicant: Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

Inventor： Masakazu Shigemori ,  Koji Sushihara ,  Kenji Murata

IPC: H03M1/34

CPC classification number: H03M1/0624 ,  H03M1/206 ,  H03M1/365

Abstract: The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

Abstract translation: 传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。 然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比 根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

公开(公告)号：US20090278716A1

公开(公告)日：2009-11-12

申请号：US12436289

申请日：2009-05-06

Applicant: Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

Inventor： Shoji KAWAHITO ,  Zheng LIU ,  Yasuhide SHIMIZU ,  Kuniyuki TANI ,  Akira KURAUCHI ,  Koji SUSHIHARA ,  Koichiro MASHIKO

IPC: H03M1/10 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1009 ,  G11C27/026 ,  H03M1/1215

Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Abstract translation: 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。