公开(公告)号：US20220189827A1

公开(公告)日：2022-06-16

申请号：US17652346

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L21/8229 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11578

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

公开(公告)号：US20240088031A1

公开(公告)日：2024-03-14

申请号：US17930656

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Bo Zhao ,  Jeffrey D. Runia ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

Abstract: A microelectronic device includes a stack structure including a block region and a non-block region. The block region includes blocks separated from one another in a first horizontal direction by insulative slot structures and each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks has stadium structures individually including staircase structures having steps comprising edges of some of the tiers. The non-block region neighbors the block region in the first horizontal direction. The non-block region includes additional stadium structures individually terminating at a relatively higher vertical position within the stack structure than at least one of the stadium structures at least partially within boundaries thereof in a second horizontal direction orthogonal to the first horizontal direction. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230063178A1

公开(公告)日：2023-03-02

申请号：US17564633

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Matthew J. King ,  Jason Reece ,  Michael J. Gossman ,  Shruthi Kumara Vadivel ,  Martin J. Barclay ,  Lifang Xu ,  Joel D. Peterson ,  Matthew Park ,  Adam L. Olson ,  David A. Kewley ,  Xiaosong Zhang ,  Justin B. Dorhout ,  Zhen Feng Yow ,  Kah Sing Chooi ,  Tien Minh Quan Tran ,  Biow Hiem Ong

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

公开(公告)号：US11690234B2

公开(公告)日：2023-06-27

申请号：US17652346

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L27/00 ,  H01L21/8229 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: H01L21/8229 ,  H01L21/76822 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L21/76877

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

公开(公告)号：US11114379B2

公开(公告)日：2021-09-07

申请号：US15995475

申请日：2018-06-01

Applicant: Micron Technology, Inc.

Inventor： Michael J. Gossman ,  M. Jared Barclay ,  Matthew J. King ,  Eldon Nelson ,  Matthew Park ,  Jason Reece ,  Lifang Xu ,  Bo Zhao

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11529

Abstract: A method used in forming integrated circuitry comprises forming a stack of vertically-alternating tiers of different composition materials. A stair-step structure is formed into the stack and an upper landing is formed adjacent and above the stair-step structure. The stair-step structure is formed to comprise vertically-alternating tiers of the different composition materials. A plurality of stairs individually comprise two of the tiers of different composition materials. At least some of the stairs individually have only two tiers that are each only of a different one of the different composition materials. An upper of the stairs that is below the upper landing comprises at least four of the tiers of different composition materials. Structure independent of method is disclosed.

公开(公告)号：US11282747B2

公开(公告)日：2022-03-22

申请号：US16799254

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L27/00 ,  H01L21/8229 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11578

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

公开(公告)号：US20210265216A1

公开(公告)日：2021-08-26

申请号：US16799254

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L21/8229 ,  H01L21/768

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within of the staircase region.