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1.
公开(公告)号:US20240257875A1
公开(公告)日:2024-08-01
申请号:US18420201
申请日:2024-01-23
Applicant: Micron Technology, Inc.
Inventor: Richard T. Housley , Quinn L. Roberts , Shruthi Kumara Vadivel , Harsh Narendrakumar Jain , Tien Minh Quan Tran , Zhen Feng Yow , Wei Deng Leong , Kah Sing Chooi , Nils Monserud
CPC classification number: G11C16/0483 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers of different compositions relative one another. The stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. A registration mark is formed in the scribe-line area. The registration mark comprises parallel first bars atop the stack having first spaces therebetween. A masking material is directly above the stack, the first bars, and the first spaces. The masking material comprises parallel second bars having second spaces therebetween. The second spaces individually have width that is less than width of individual of the second bars. Some of the masking material is spaced laterally-outward of the second bars. Vertical thickness of the some masking material that is laterally-outward of the second bars have a vertical thickness laterally-outward of the first spaces that is greater than vertical thickness of the second bars. Ratio of the vertical thickness of the some masking material that is laterally-outward of the second bars divided by the width of the second bars is 6.0 to 9.6. After forming the registration mark, the first bars and the first and second tiers in the scribe-line area are cut through to form individual die that individually comprise one of the individual die areas. Other embodiments, including structure independent of method, are disclosed.
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2.
公开(公告)号:US20230063178A1
公开(公告)日:2023-03-02
申请号:US17564633
申请日:2021-12-29
Applicant: Micron Technology, Inc.
Inventor: Bo Zhao , Matthew J. King , Jason Reece , Michael J. Gossman , Shruthi Kumara Vadivel , Martin J. Barclay , Lifang Xu , Joel D. Peterson , Matthew Park , Adam L. Olson , David A. Kewley , Xiaosong Zhang , Justin B. Dorhout , Zhen Feng Yow , Kah Sing Chooi , Tien Minh Quan Tran , Biow Hiem Ong
IPC: H01L23/528 , H01L23/522 , H01L21/768
Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.
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