公开(公告)号：US20210043525A1

公开(公告)日：2021-02-11

申请号：US16535882

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James E. Davis

IPC: H01L21/66 ,  H01L27/11556 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US08767467B2

公开(公告)日：2014-07-01

申请号：US13970055

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Krishna K. Parat ,  Akira Goda ,  Koichi Kawal ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC: G11C16/04

CPC classification number: G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Abstract translation: 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US11424169B2

公开(公告)日：2022-08-23

申请号：US16535882

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James E. Davis

IPC: H01L23/528 ,  G11C16/26 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US20230005799A1

公开(公告)日：2023-01-05

申请号：US17892749

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Kenneth William Marr ,  Brian J. Soderling ,  Michael P. Violette ,  Joshua Daniel Tomayer ,  James Eric Davis

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H03K3/03 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C29/14 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

公开(公告)号：US20130332769A1

公开(公告)日：2013-12-12

申请号：US13970055

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC: G11C29/00

CPC classification number: G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Abstract translation: 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。