公开(公告)号：US12051458B2

公开(公告)日：2024-07-30

申请号：US17713641

申请日：2022-04-05

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Christopher Joseph Bueb

IPC: G11C11/406 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C5/148 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. The memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. The memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. In some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. The memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.

公开(公告)号：US20240160386A1

公开(公告)日：2024-05-16

申请号：US18492569

申请日：2023-10-23

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Aravind Ramamoorthy ,  Anand Mudlapur ,  Zheng Wang ,  Olivier Duval

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0679

Abstract: Methods, systems, and devices for variable density storage device are described. A memory system may receive a write command to write data to the memory system. The memory system may write the data to a first set of memory cells of the memory system using a first write operation based on receiving the write command. The first set of memory cells store three or fewer bits of information in a single memory cell. The memory system may identify whether to transfer the data to a second set of memory cells on one or more parameters associated with the data. The second set of memory cells may store more bits of information in a single memory cell than the first set of memory cells. The memory system may transfer the data to the second set of memory cells based on identifying that the data is to be transferred.

公开(公告)号：US20240061605A1

公开(公告)日：2024-02-22

申请号：US17888982

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Gianluca Coppola ,  Ryan Laity ,  Christopher Joseph Bueb

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for priority information are described. A memory system may be configured to receive, at a memory system, an indication that data is critical to operating the memory system; receive the data that is critical to operating the memory system based at least in part on the indication; select one more parameters to provide a reliability of a storage of the data into a memory device of the memory system based at least in part on receiving the indication and receiving the data; and program the data into the memory device of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.

公开(公告)号：US11875039B2

公开(公告)日：2024-01-16

申请号：US17456980

申请日：2021-11-30

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2211/007

Abstract: Methods, systems, and devices for temperature-based scrambling for error control in memory systems are described. Techniques are described for a memory system to scramble data using different scrambling code parameters when writing the data at different temperatures. Scrambling the data using scrambling code parameters that are based on the temperatures at the time or writing the data may reduce errors introduced into the data by operating the memory cells at extreme temperatures.

公开(公告)号：US11663153B2

公开(公告)日：2023-05-30

申请号：US17326141

申请日：2021-05-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1605

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

公开(公告)号：US11573708B2

公开(公告)日：2023-02-07

申请号：US16452341

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G06F11/20

Abstract: A solid state drive having at least one component solid state drive, a spare solid state drive, and a drive aggregator. The drive aggregator has at least one host interface, at least one drive interface connected to the at least one component solid state drive, and an interface connected to the spare solid state drive. The drive aggregator is configured to maintain, in the spare solid state drive, a copy of a dataset that is stored in the component solid state drive. In response to a failure of the component solid state drive, the drive aggregator is configured to substitute a function of the component solid state drive with respect to the dataset with a corresponding function of the spare solid state drive, based on the copy of the dataset maintained in the spare solid state drive.

公开(公告)号：US11500766B2

公开(公告)日：2022-11-15

申请号：US17170766

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Poorna Kale

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F13/38 ,  G06F12/10 ,  G06F13/40

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

公开(公告)号：US11354262B2

公开(公告)日：2022-06-07

申请号：US17180623

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F12/10

Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

公开(公告)号：US12260114B2

公开(公告)日：2025-03-25

申请号：US17888982

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Gianluca Coppola ,  Ryan Laity ,  Christopher Joseph Bueb

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for priority information are described. A memory system may be configured to receive, at a memory system, an indication that data is critical to operating the memory system; receive the data that is critical to operating the memory system based at least in part on the indication; select one more parameters to provide a reliability of a storage of the data into a memory device of the memory system based at least in part on receiving the indication and receiving the data; and program the data into the memory device of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.

公开(公告)号：US12205627B2

公开(公告)日：2025-01-21

申请号：US17811230

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Minjian Wu

IPC: G11C11/406 ,  G11C11/4072

Abstract: Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.