公开(公告)号：US20230236930A1

公开(公告)日：2023-07-27

申请号：US17828475

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Marc SFORZIN ,  Paolo AMATO ,  Daniele BALLUCHI

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2201/805

Abstract: A system and method for memory error recovery in CXL components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.

公开(公告)号：US20250094278A1

公开(公告)日：2025-03-20

申请号：US18778665

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Emanuele CONFALONIERI ,  Daniele BALLUCHI ,  Danilo CARACCIO ,  Nicola DEL GATTO ,  Rishabh DUBEY

IPC: G06F11/10

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

公开(公告)号：US20230236753A1

公开(公告)日：2023-07-27

申请号：US17854639

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Angelo VISCONTI ,  Giorgio SERVALLI ,  Daniele BALLUCHI ,  Paolo AMATO

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0673

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.