公开(公告)号：US20230236753A1

公开(公告)日：2023-07-27

申请号：US17854639

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Angelo VISCONTI ,  Giorgio SERVALLI ,  Daniele BALLUCHI ,  Paolo AMATO

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0673

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.

公开(公告)号：US20230259424A1

公开(公告)日：2023-08-17

申请号：US17883399

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Paolo AMATO

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/1076

Abstract: Provided is a computing system including a memory system in communication with a host, and for storing data therein and the memory system includes a memory having a plurality of memory components and a memory array and coupled to the controller via a memory interface. Each memory component includes a memory cyclic-redundancy-check (CRC) engine that performs a CRC check of data during read and write operations between the host and the memory array. The memory system also includes a controller that has a plurality of controller CRC engines and communicates with the memory components to control data transmission between the memory, the host and the memory array.

公开(公告)号：US20230236930A1

公开(公告)日：2023-07-27

申请号：US17828475

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Marc SFORZIN ,  Paolo AMATO ,  Daniele BALLUCHI

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2201/805

Abstract: A system and method for memory error recovery in CXL components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.

公开(公告)号：US20230231578A1

公开(公告)日：2023-07-20

申请号：US17894777

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Paolo AMATO

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/159 ,  H03M13/617

Abstract: There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

公开(公告)号：US20230229554A1

公开(公告)日：2023-07-20

申请号：US17894742

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Marc SFORZIN ,  Paolo AMATO

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/0772

Abstract: There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.