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公开(公告)号：US20250028449A1
公开(公告)日：2025-01-23
申请号：US18806275
申请日：2024-08-15
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Donald Martin Morgan
IPC: G06F3/06
Abstract: Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.
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公开(公告)号：US20230068011A1
公开(公告)日：2023-03-02
申请号：US17895565
申请日：2022-08-25
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara , Yusuke Yono , Donald Martin Morgan , Nobuo Yamamoto
Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.
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公开(公告)号：US11462249B2
公开(公告)日：2022-10-04
申请号：US16916612
申请日：2020-06-30
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara , Yusuke Jono , Donald Martin Morgan , Nobuo Yamamoto
Abstract: Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.
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公开(公告)号：US20220066893A1
公开(公告)日：2022-03-03
申请号：US17005027
申请日：2020-08-27
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald Martin Morgan
Abstract: Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.
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公开(公告)号：US20240038284A1
公开(公告)日：2024-02-01
申请号：US17877592
申请日：2022-07-29
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Alan J. Wilson , Donald Martin Morgan
CPC classification number: G11C7/24 , G11C7/1063 , G11C7/1066
Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.
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Patent Agency Ranking
公开(公告)号：US20230028060A1
公开(公告)日：2023-01-26
申请号：US17873862
申请日：2022-07-26
Applicant: Micron Technology, Inc.
Inventor： Donald Martin Morgan
Abstract: Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.
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公开(公告)号：US20210407556A1
公开(公告)日：2021-12-30
申请号：US16916612
申请日：2020-06-30
Applicant: Micron Technology, Inc.
Inventor： Yasushi Matsubara , Yusuke Jono , Donald Martin Morgan , Nobuo Yamamoto
Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.
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公开(公告)号：US20250006236A1
公开(公告)日：2025-01-02
申请号：US18882436
申请日：2024-09-11
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Alan J. Wilson , Donald Martin Morgan
Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.
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公开(公告)号：US12118211B2
公开(公告)日：2024-10-15
申请号：US18100803
申请日：2023-01-24
Applicant: Micron Technology, Inc.
Inventor： Donald Martin Morgan , Alan J. Wilson
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/0644 , G06F3/0679
Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.
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公开(公告)号：US12112831B2
公开(公告)日：2024-10-08
申请号：US17877592
申请日：2022-07-29
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Alan J. Wilson , Donald Martin Morgan
CPC classification number: G11C7/24 , G11C7/1063 , G11C7/1066 , G11C8/20
Abstract: Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.
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