公开(公告)号：US12086015B2

公开(公告)日：2024-09-10

申请号：US17575334

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G11C16/26 ,  G06F1/3296 ,  G06F12/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/30 ,  H10B41/30 ,  H10B41/40 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F12/0238 ,  G11C5/147 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/26 ,  G11C16/30 ,  H10B41/30 ,  H10B41/40 ,  G06F1/3275 ,  G11C2207/2227

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

公开(公告)号：US10719241B2

公开(公告)日：2020-07-21

申请号：US15990497

申请日：2018-05-25

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley ,  David Matthew Springberg ,  Dustin James Carter

IPC: G06F13/42 ,  G06F3/06

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

公开(公告)号：US20190295608A1

公开(公告)日：2019-09-26

申请号：US16438311

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G11C5/14 ,  G06F1/28 ,  G06F1/26

Abstract: A power management integrated circuit (PMIC) receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the PMIC generates an interrupt signal causing the memory system to shut down safely without data loss.

公开(公告)号：US10423218B1

公开(公告)日：2019-09-24

申请号：US15919036

申请日：2018-03-12

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/3296 ,  G06F12/02 ,  G11C16/26 ,  G11C16/30 ,  H01L27/11526 ,  G11C7/20 ,  G11C7/22 ,  H01L27/11521 ,  G11C5/14

Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

公开(公告)号：US20190278516A1

公开(公告)日：2019-09-12

申请号：US15919026

申请日：2018-03-12

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F3/06 ,  G11C5/14

Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

公开(公告)号：US11513734B2

公开(公告)日：2022-11-29

申请号：US17066305

申请日：2020-10-08

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C5/14

Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

公开(公告)号：US10891062B2

公开(公告)日：2021-01-12

申请号：US16211048

申请日：2018-12-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Matthew Springberg ,  Matthew David Rowley ,  Peter Edward Kaineg

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.

公开(公告)号：US20200348856A1

公开(公告)日：2020-11-05

申请号：US16932116

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley ,  David Matthew Springberg ,  Dustin James Carter

IPC: G06F3/06 ,  G06F13/42

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

公开(公告)号：US20200075062A1

公开(公告)日：2020-03-05

申请号：US16676846

申请日：2019-11-07

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/28

Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.

公开(公告)号：US20190278364A1

公开(公告)日：2019-09-12

申请号：US16395974

申请日：2019-04-26

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley

IPC: G06F1/3296 ,  G11C5/14 ,  H01L27/11521 ,  G11C7/22 ,  G06F12/02 ,  H01L27/11526 ,  G11C16/30 ,  G11C16/26 ,  G11C7/20

Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.